MFMIS Ferroelectric Transistor Structure for High-Endurance Integration
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Solution Overview
Problem
Current semiconductor devices, particularly DRAM devices, face challenges in reducing transistor and capacitor sizes for increased integration while maintaining endurance, as ferroelectric field effect transistors (FeFETs) with metal-ferroelectric-insulator-semiconductor (MFIS) structures have poor endurance due to charge trapping issues and are unsuitable for high-cycle applications.
Innovation Solution
The semiconductor device incorporates a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure with a specific capacitance ratio between the ferroelectric and insulating layers, adjusting the area and thickness of these layers to reduce charge trapping and enhance endurance, allowing for a high degree of integration and endurance of over 10^10 cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of capacitors and transistors is reduced to increase integration density, then the degree of integration is improved, but the endurance deteriorates due to charge trapping phenomena
Solution Approach 1:
The patent changes the physical parameters of the device structure by introducing a floating gate electrode layer between the control gate and semiconductor layer, and by optimizing the thickness and material composition of the insulating layer. This structural parameter change enables simultaneous achievement of small device size for high integration and sufficient charge storage capacity for high endurance
Solution Approach 2:
The patent employs a composite structure combining multiple materials: ferroelectric layer for non-volatile memory function, insulating layer for charge isolation, and floating gate electrode layer for charge storage. This composite material approach resolves the contradiction by distributing different functions across different material layers, enabling both high integration and high endurance
2Ease of manufacture
If FeFETs with MFIS structure are used to eliminate capacitors for easier stacking, then the ease of manufacture is improved, but the endurance deteriorates due to charge trapping in the insulating layer
Solution Approach 1:
The floating gate electrode layer acts as an intermediary between the control gate and semiconductor layer, mediating the charge storage function. This intermediary structure prevents direct charge trapping in the insulating layer by providing an alternative charge storage location, thereby improving endurance while maintaining the capacitor-less FeFET structure for ease of stacking
Solution Approach 2:
The patent segments the gate structure into a control gate electrode layer and a floating gate electrode layer separated by an insulating layer. This segmentation allows the control gate to apply voltage without direct contact with the semiconductor layer, preventing charge trapping and improving endurance while maintaining the simplified FeFET structure
3Reliability
If the ratio of ferroelectric layer capacitance to insulating layer capacitance is adjusted to reduce charge trapping, then the endurance is improved, but the device complexity increases due to process difficulty
Solution Approach 1:
The patent optimizes the thickness parameters of the insulating layer and ferroelectric layer to achieve the desired capacitance ratio. By carefully controlling these dimensional parameters during fabrication, the patent achieves low charge trapping and high endurance without requiring complex multi-step processes or specialized equipment
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the endurance and integration of semiconductor devices by optimizing the capacitance ratio and layer dimensions, enabling reliable operation in high-cycle applications without increasing process complexity.
Implementation Method 1
the ratio of ferroelectric layer capacitance CFE between a control gate electrode layer and a floating gate electrode layer, which are apart from each other with a ferroelectric layer therebetween, and insulating layer capacitance CDE between the floating gate electrode layer and a semiconductor layer
Data Source
AI summary
A semiconductor device includes a semiconductor layer extending in a first direction and including a source region and a drain region, which are apart from each other in the first direction; an insulating layer surrounding the semiconductor layer; a first gate electrode layer surrounding the insulating layer; a ferroelectric layer provided on the first gate electrode layer; and a second gate electrode layer provided on the ferroelectric layer.