GAA Nanowire Superlattice With Abrupt Si/SiGe Etch Interfaces
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Solution Overview
Problem
The semiconductor industry faces challenges in further shrinking the size and increasing the speed of field-effect transistors, particularly with the implementation of finFETs, due to new device structure complexities.
Innovation Solution
The formation of a Gate All-Around (GAA) transistor using a superlattice structure with alternating layers of SiGe and Si, where precise control of dopant implantation and deposition processes creates highly controlled diffusion interfaces, enabling improved etching selectivity and the formation of horizontal nanowires with uniform diameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If finFET structure is implemented to shrink transistor size, then transistor dimensions are reduced, but device structure complexity increases
Solution Approach 1:
The channel region is segmented into multiple horizontal nanowires stacked vertically, with each nanowire providing a separate conduction path. This segmentation allows the transistor to achieve three-dimensional gate control while maintaining manufacturability through standardized deposition and etching processes.
Solution Approach 2:
The invention transitions from planar two-dimensional gate control to three-dimensional gate-all-around control by forming horizontal nanowires stacked in the vertical dimension. This dimensional change enables the gate to control the channel from all directions, improving device performance while managing structural complexity.
2Length of moving object
If continuous shrinking of transistor dimensions is pursued, then transistor size decreases, but manufacturing precision requirements increase
Solution Approach 1:
Alternating layers of SiGe and Si are deposited in advance before any etching or doping processes. This preliminary formation of compositionally distinct layers creates well-defined diffusion interfaces that are less sensitive to subsequent processing variations, thereby reducing manufacturing precision requirements.
Solution Approach 2:
The invention utilizes changes in material composition (Si vs. SiGe) to create distinct diffusion barriers and interfaces. By controlling the germanium content and layer thicknesses, precise diffusion profiles are achieved without requiring extremely tight control of processing parameters.
3Reliability
If Gate All-Around structure is formed with horizontal nanowires, then gate control is improved, but etching selectivity requirements increase
Solution Approach 1:
The channel structure is formed as a composite of alternating Si and SiGe layers, where the different materials provide both the desired gate control and the etching selectivity. The SiGe layers can be selectively removed or retained based on device type, enabling precise control of the nanowire formation process.
Solution Approach 2:
Different regions of the structure have different material compositions tailored to specific functions: Si layers provide the primary conduction channels while SiGe layers provide etching contrast and can be selectively removed to form either NFET or PFET devices. This local differentiation simplifies the etching process while maintaining excellent gate control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the fabrication of transistors with enhanced performance by maintaining precise control over diffusion interfaces, improving etching selectivity, and enabling the formation of horizontal nanowires with consistent dimensions, addressing the scaling and speed challenges in transistor development.
Implementation Method 1
precise control of dopant implantation and deposition processes creates highly controlled diffusion interfaces
Data Source
AI summary
Methods are disclosed for forming a multi-layer structure including highly controlled diffusion interfaces between alternating layers of different semiconductor materials. According to embodiments, during a deposition of semiconductor layers, the process is controlled to remain at low temperatures such that an inter-diffusion rate between the materials of the deposited layers is managed to provide diffusion interfaces with abrupt Si/SiGe interfaces. The highly controlled interfaces and first and second layers provide a multi-layer structure with improved etching selectivity. In an embodiment, a gate all-around (GAA) transistor is formed with horizontal nanowires (NWs) from the multi-layer structure with improved etching selectivity. In embodiments, horizontal NWs of a GAA transistor may be formed with substantially the same size diameters and silicon germanium (SiGe) NWs may be formed with “all-in-one” silicon (Si) caps.