Lateral GAA-FET Spacer Formation With Self-Aligned Dummy Gates
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Solution Overview
Problem
Conventional semiconductor manufacturing processes for lateral GAA-FETs face challenges in achieving precise alignment and consistent thickness of spacers, requiring high etching precision and process variation control, which is difficult to maintain in large-scale production.
Innovation Solution
A method where a semiconductor laminated structure with alternately stacked channel and sacrificial layers is formed, and dummy gate layers are created to form a fin structure, with spacers being simultaneously formed at both ends using the same process step, ensuring consistent thickness and self-alignment through shared process parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate processes are used to form outer spacers and inner spacers, then alignment precision can be maintained, but manufacturing complexity and process variation control become extremely difficult
Solution Approach 1:
The patent merges the formation of outer spacers and inner spacers into a single manufacturing process step. By using a unified spacer formation process that simultaneously creates both outer spacers (on dummy gate layers) and inner spacers (in grooves between channel layers), the patent eliminates the need for separate alignment processes while maintaining consistent spacing dimensions across all structures.
Solution Approach 2:
The patent creates a universal spacer formation process that serves multiple functions simultaneously: forming outer spacers for gate alignment, forming inner spacers for structural definition, and establishing consistent spacing dimensions. This multi-functional approach replaces what would traditionally require multiple specialized processes.
2Manufacturing precision
If high etching precision is used to form grooves for inner spacers, then alignment between spacers is improved, but process variation control becomes extremely challenging
Solution Approach 1:
The patent employs self-aligned spacer formation where the spacer structures automatically position themselves relative to the channel layers and dummy gate layers through the unified formation process. This self-alignment mechanism eliminates the need for high-precision etching to create grooves, as the spacers form concurrently with their reference structures, naturally maintaining alignment without requiring extreme etching precision.
3Manufacturing precision
If multiple separate processes are used for different spacers, then alignment can be ensured, but manufacturing time and productivity are reduced
Solution Approach 1:
The patent combines multiple spacer formation operations into a single process step, forming both outer spacers and inner spacers simultaneously. This merging of processes dramatically reduces the total number of manufacturing steps required, thereby increasing production throughput and productivity while maintaining consistent alignment through the unified process approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces variations in gate length and other components, and adapts well to large-scale industrial production by ensuring consistent spacer thickness and alignment without the need for separate processes for different spacers.
Implementation Method 1
forming a semiconductor laminated structure on a substrate, where the semiconductor laminated structure includes channel layers and sacrificial layers that are alternately stacked
Implementation Method 2
manufacturing dummy gate layers at positions at which the sacrificial layers are removed and on a surface of the channel layer at the top layer
Implementation Method 3
polysilicon at two ends of the dummy gate layer is adjusted to silicon nitride by using a same subsequent process step, to form the spacer
Implementation Method 4
simultaneously performing oxidation on two ends of each of the dummy gate layers to form initial spacers
Data Source
AI summary
The present disclosure relates to semiconductor devices, manufacturing methods, and electronic devices. One example semiconductor device manufacturing method includes forming a semiconductor laminated structure on a substrate. The semiconductor laminated structure includes channel layers and sacrificial layers that are alternately stacked. At least part of the sacrificial layers are removed. Dummy gate layers are manufactured at positions at which the sacrificial layers are removed and on a surface of the channel layer at a top layer to form a fin structure. A same process step is used to simultaneously form spacers at two ends of the dummy gate layers.