Multi-Gate Isolation Recess for Bottom-Channel Gate Control
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Solution Overview
Problem
Multi-gate transistors, such as gate-all-around (GAA) FETs, face issues with poor gate control and increased capacitance due to sub-threshold leakage current and short-channel effects, particularly in the region near the bottommost channel layer, which are exacerbated by thick shallow trench isolation structures.
Innovation Solution
A method for forming semiconductor devices involves creating a SiGe capping layer over the fins, allowing Ge to diffuse into isolation features to form a Ge-doped layer, followed by etching to recess the isolation features, enabling a metal gate stack to directly contact the sidewalls of the semiconductor fin, thereby improving gate control and reducing leakage current and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thick shallow trench isolation structures are used to separate semiconductor fins, then isolation and electrical separation are improved, but gate control deteriorates and capacitance increases in the sub-channel region
Solution Approach 1:
The patent applies local quality by creating a recessed isolation structure only in the sub-channel region where gate control is needed, while maintaining full isolation thickness in other regions. This allows the isolation structure to provide electrical separation where needed while removing material in the sub-channel region to enable direct gate contact with the semiconductor fin, thus resolving the contradiction between isolation effectiveness and gate control
2Reliability
If thick shallow trench isolation structures are used, then electrical separation is improved, but leakage current increases due to poor gate control
Solution Approach 1:
The recessed isolation structure creates a local variation in isolation thickness, providing full isolation elsewhere while creating a thin or absent isolation layer in the sub-channel region. This enables the metal gate stack to directly contact the semiconductor fin sidewalls, improving gate control and reducing leakage current while maintaining electrical separation in other regions
3Ease of operation
If isolation features are recessed to improve gate control, then gate control and performance are improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the recessed isolation structure before completing the metal gate stack formation. The isolation recesses are created in the sub-channel region prior to depositing the gate electrode materials, which simplifies the overall process by establishing the gate-fin contact geometry early in the fabrication sequence rather than requiring complex post-processing steps
Solution Approach 2:
The isolation structure is segmented into regions of different thicknesses - full thickness isolation in non-sub-channel regions and recessed or removed isolation in sub-channel regions. This segmentation allows the structure to simultaneously provide electrical separation and enable direct gate contact, achieving improved gate control without requiring complete removal of isolation structures throughout the entire device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances gate control in the sub-channel region, reduces leakage current, and minimizes capacitance, leading to improved performance of GAA FETs by ensuring the metal gate stack effectively engages with the semiconductor fin.
Implementation Method 1
depositing a capping layer including SiGe over the semiconductor fins, where Ge in the capping layer diffuses into the isolation features to form a Ge-doped layer in the isolation features
Data Source
AI summary
A semiconductor structure includes a stack of semiconductor layers disposed over a protruding portion of a substrate, isolation features disposed over the substrate, wherein a top surface of the protruding portion of the substrate is separated from a bottom surface of the isolation features by a first distance, a metal gate stack interleaved with the stack of semiconductor layers, where a bottom portion of the metal gate stack is disposed on sidewalls of the protruding portion of the substrate and where thickness of the bottom portion of the metal gate stack is defined by a second distance that is less than the first distance, and epitaxial source/drain features disposed adjacent to the metal gate stack.