GAA SRAM Cell Structure With Mixed Threshold Voltages for Multi-Use Chips
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Solution Overview
Problem
Designing multi-application memory chips with optimized performance characteristics is challenging due to competing demands for space and performance in advanced IC technology nodes, particularly with gate-all-around (GAA) transistors, which have complex structures and are costly to develop.
Innovation Solution
A memory chip structure that includes multiple GAA-based memory cells, each optimized for different applications such as high-speed, low-power, and superhigh-speed operations, sharing similar structures but with adjustable physical dimensions and material compositions to achieve tailored performance characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If GAA transistors are incorporated into SRAM to reduce chip footprint, then area efficiency is improved, but device complexity increases
Solution Approach 1:
The patent divides the SRAM array into multiple banks, where each bank contains memory cells with different transistor configurations (planar and GAA). This segmentation allows selective use of GAA transistors in specific regions to achieve area reduction while maintaining simpler planar transistors in other regions to manage complexity.
Solution Approach 2:
Different regions of the SRAM array are assigned different transistor types optimized for different functions. GAA transistors are used in specific banks or regions where high density is critical, while planar transistors are used in regions requiring simpler fabrication or different performance characteristics.
2Adaptability or versatility
If SRAM is designed for multiple applications with different performance characteristics, then adaptability is improved, but design complexity increases
Solution Approach 1:
The patent creates a universal SRAM array structure that can serve multiple applications by incorporating different transistor types within the same array. The array can be configured to support high-speed applications, low-power applications, or a combination thereof, depending on which transistor regions are activated and how they are interconnected.
Solution Approach 2:
The SRAM array enables dynamic configuration where different banks or regions with different transistor characteristics can be selectively activated based on the specific application requirements. This allows the same physical structure to adapt its performance characteristics dynamically.
3Adaptability or versatility
If multiple memory cells with different performance characteristics are integrated on the same chip, then versatility is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the fabrication process into distinct stages where different transistor types are formed in different regions. By using separate processing steps for planar and GAA transistor formation, the patent reduces the precision requirements for each individual step compared to forming all transistor types simultaneously.
Solution Approach 2:
The patent introduces intermediary structures and processing steps that facilitate the formation of different transistor types. These intermediaries act as templates or guides that simplify the fabrication process and reduce precision requirements by breaking down complex multi-step processes into manageable stages.
Data Source
AI summary
An exemplary semiconductor memory chip includes a first static random access memory (SRAM) cell and a second SRAM cell. The first SRAM cell has a first GAA transistor, and the second SRAM cell has a second GAA transistor. The first and the second SRAM cells have a same cell size, and the first and the second GAA transistors are of a same transistor type. Moreover, the first GAA transistor has a first threshold voltage and the second GAA transistor has a second threshold voltage. The second threshold voltage is different than the first threshold voltage. Furthermore, the first GAA transistor has a first gate stack and the second GAA transistor has a second gate stack. The first gate stack has a first work function value, and the second gate stack has a second work function value. The second work function value is different than the first work function value.