GAA Transistor Structure Using a Self-Aligned Oxide Mask

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Solution Overview

Problem

The integration of gate-all-around (GAA) transistor fabrication in semiconductor manufacturing is challenging due to complexity and alignment issues, which hinders the production of smaller, faster, and more efficient electronic devices.

Innovation Solution

A method involving the formation of nanowire structures with self-aligned mask layers, where a Si layer and SiGe layer are grown over the source/drain structures, oxidized to form an oxide layer, and used as a mask for subsequent processes, simplifying the manufacturing process and reducing misalignment risks, allowing for the formation of gate-all-around transistor structures without complex alignment procedures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional multi-step alignment processes are used for GAA fabrication, then manufacturing precision can be maintained, but device complexity and process difficulty increase significantly

Engineering Contradiction:
Improvealignment precisionVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The method performs preliminary actions by forming the Si layer and SiGe layer with self-aligned growth before the actual gate patterning. The SiGe layer is oxidized in advance to create the mask layer, which automatically aligns with the source/drain structures. This preliminary preparation eliminates the need for subsequent complex alignment steps, resolving the contradiction between maintaining precision and reducing process complexity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The SiGe layer serves itself as a mask material after oxidation, and the oxidized SiGe mask automatically positions itself relative to the source/drain structures through self-aligned growth. The process uses the deposited layers' own properties to define the gate pattern without requiring external alignment procedures, thereby simplifying the overall fabrication process while maintaining precision.

Inventive Principle:
Principle #25Self-service

2Ease of manufacture

If self-aligned mask formation is implemented, then ease of manufacture improves, but additional material deposition steps are required

Engineering Contradiction:
Improvefabrication simplicityVSAvoidprocess steps
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The SiGe layer performs multiple functions: it serves as a deposition layer during epitaxial growth, acts as a precursor for the mask formation through oxidation, and defines the gate pattern boundaries. By making the SiGe layer multi-functional, the process adds material deposition steps but eliminates the need for separate mask fabrication and alignment procedures, ultimately improving ease of manufacture.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The method merges the mask formation step with the epitaxial growth process. The SiGe layer is deposited concurrently with the source/drain structures, and its subsequent oxidation integrates mask creation into the existing process flow. This merging reduces the number of discrete process steps and simplifies fabrication, addressing the contradiction between ease of manufacture and process complexity.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If gate-all-around structures are fabricated with precise alignment, then transistor performance improves, but production time increases

Engineering Contradiction:
Improvetransistor performanceVSAvoidproduction efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The self-aligned mask is formed in advance during the epitaxial growth phase, before gate patterning begins. This preliminary positioning ensures that the gate will be precisely aligned with the source/drain structures, guaranteeing high transistor performance. Meanwhile, eliminating subsequent alignment steps reduces production time, thereby resolving the contradiction between reliability and productivity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The oxidized SiGe mask automatically positions itself relative to the channel and source/drain regions through self-aligned growth mechanisms. This self-positioning ensures precise gate alignment for high-performance transistors without requiring time-consuming external alignment procedures, thus maintaining productivity while achieving reliable device performance.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach simplifies the semiconductor manufacturing process, improves yield, and enhances performance by eliminating the need for complicated alignment processes and reducing misalignment risks, enabling the production of high-performance GAA transistors.

Implementation Method 1

oxidized to form an oxide layer

Methodology Applied
Scientific EffectOxidation: Oxidation

Data Source

PatentUS12119404B2Gate all around structure with additional silicon layer and method for forming the same
Publication Date: 2024.10.15 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12119404B2 patent drawing
  • US12119404B2 patent drawing
  • US12119404B2 patent drawing

AI summary

Methods for manufacturing a semiconductor structure are provided. The method includes alternately stacking first semiconductor material layers and second semiconductor layers over a substrate and patterning the first semiconductor material layers and the second semiconductor layers to form a first fin structure and a second fin structure. The method also includes forming an insulating layer around the first fin structure and the second fin structure and forming a dielectric fin structure over the insulating layer and spaced apart from the first fin structure and the second fin structure. The method also includes forming a first source/drain structure attached to the first fin structure and forming a semiconductor layer covering the first source/drain structure. The method also includes oxidizing the semiconductor layer to form an oxide layer and forming a second source/drain structure attached to the second fin structure after the oxide layer is formed.