ONNO Memory Transistor Structure for Charge Retention and CMOS Integration
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Solution Overview
Problem
Conventional memory transistors suffer from poor data retention and limited transistor lifetime due to leakage currents through insulating layers, and existing processes for forming memory transistors are often incompatible with those used for logic transistors in integrated circuits, particularly in System-On-Chip applications.
Innovation Solution
A memory transistor with a polysilicon channel region and an oxide-nitride-nitride-oxide (ONNO) stack, including a multi-layer charge-trapping region with an oxygen-rich first nitride layer and an oxygen-lean second nitride layer, along with a high work function gate electrode, is used to enhance data retention and compatibility with logic transistor fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a conventional charge trapping layer is used in memory transistors, then the initial program-erase window is large, but the data retention time is poor due to rapid charge loss through leakage current
Solution Approach 1:
The charge trapping layer is divided into multiple discrete layers (first charge trapping layer, second charge trapping layer, third charge trapping layer) separated by tunnel insulating layers. This segmentation allows each layer to contribute to charge storage while the insulating layers prevent charge loss, achieving both high initial capacity and long retention time
Solution Approach 2:
The memory transistor employs a composite structure combining multiple materials with different properties: polysilicon layers for charge trapping, silicon oxide for tunnel insulating, and silicon nitride for blocking insulating. This composite approach enables simultaneous achievement of high charge storage capacity and low leakage current
2Quantity of substance
If the charge trapping layer is made silicon-rich to increase initial window, then the window collapses rapidly reducing transistor lifetime
Solution Approach 1:
The charge trapping functionality is segmented across multiple polysilicon layers separated by insulating barriers. This prevents the rapid window collapse seen in single-layer silicon-rich structures by distributing charge storage across discrete, isolated trapping regions
Solution Approach 2:
Tunnel insulating layers are pre-formed between the polysilicon charge trapping layers before charge injection. This preliminary insulation structure prevents charge loss pathways from forming, maintaining reliability over the transistor lifetime
3Ease of manufacture
If existing memory transistor fabrication processes are used, then memory transistors can be formed, but they are incompatible with logic transistor fabrication processes in integrated circuits
Solution Approach 1:
The memory transistor structure uses standard polysilicon, silicon oxide, and silicon nitride materials that are universally compatible with existing logic transistor fabrication processes. The multi-layer structure can be integrated into standard CMOS工艺流程, enabling both memory and logic transistors to be fabricated on the same substrate
Solution Approach 2:
The invention uses homogeneous materials (polysilicon, silicon oxide, silicon nitride) that are already standard in the semiconductor industry. This material homogeneity ensures compatibility with existing fabrication equipment and processes used for logic transistor manufacturing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly improves data retention and extends the operating life of memory transistors by reducing charge loss and leakage currents, while allowing for the integration of both memory and logic transistors on a common substrate, enhancing the performance and efficiency of integrated circuits.
Implementation Method 1
a high work function gate electrode formed over a surface of the ONNO stack
Implementation Method 2
a multi-layer charge-trapping region including an oxygen-rich first nitride layer and an oxygen-lean second nitride layer
Implementation Method 3
an oxide-nitride-nitride-oxide (ONNO) stack disposed above the channel region
Data Source
AI summary
An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.