CFET Vertical Contact Isolation Using Self-Limiting Etch-Stop Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The manufacturing of complementary field effect transistors (CFETs) faces challenges in preventing electrical shorts due to unintentional connections and over-etching, which can lead to narrow gaps between metal contacts and silicon substrates, increasing the risk of shorts during the stacking process.
Innovation Solution
Implementing an etch-stop at the bottom of the source and/or drain epitaxy and over a buried power rail (BPR) within the CFET structure, using blocking materials and insulating layers to prevent contact between conductive materials and the silicon substrate, and employing self-limiting etching techniques to control the etching process and maintain a safe gap distance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional etching techniques are used without etch-stops, then the etching process can be simpler and faster, but electrical shorts occur due to unintentional connections between conductive materials and silicon substrate
Solution Approach 1:
Etch-stop layers are deposited in advance at critical interfaces (bottom of source/drain epitaxy and over buried power rails) before the contact etching process. This preliminary action ensures that even if etching parameters vary or over-etching occurs, the conductive material will not contact the silicon substrate, thus preventing electrical shorts without requiring complex real-time control during etching
Solution Approach 2:
Etch-stop layers act as intermediary barrier layers between the conductive contact material and the silicon substrate. These intermediate layers (such as silicon nitride or oxide) provide both physical separation and etching selectivity, allowing the etch process to proceed through other layers while being blocked at the critical interfaces, thus preventing direct contact between conductive material and substrate
2Reliability
If blocking materials are added to prevent shorts, then electrical short prevention improves, but the manufacturing process steps increase
Solution Approach 1:
The etch-stop layer deposition is merged with existing manufacturing process steps, such as combining it with the buried power rail formation process or the epitaxial growth process. By integrating the short-prevention function into existing process flows rather than adding completely separate steps, the increase in manufacturing cycle time is minimized while still achieving reliable electrical short prevention
3Manufacturing precision
If etching is performed without self-limiting techniques, then the etching process is simpler to control, but narrow gaps form between metal contacts and silicon substrate increasing short risk
Solution Approach 1:
The etch-stop layers are designed to be selectively removed only after they have served their protective function during contact formation. The self-limiting nature comes from the fact that the etch process automatically stops when it reaches the etch-stop layer, which has different etching selectivity. This self-limiting mechanism provides precise gap control without requiring complex real-time monitoring or adjustment of etching parameters
Solution Approach 2:
Different etching parameters (such as etch chemistry, power, pressure, and temperature) are optimized for different process stages. The etching process uses parameters that provide high selectivity for removing sacrificial materials while being blocked by the etch-stop layers. This parameter optimization enables precise control of the gap distance between contacts and substrate without increasing overall process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the robustness of the CFET manufacturing process by minimizing the risk of electrical shorts, ensuring a wider process margin and greater yield, and maintaining a sufficient gap distance to prevent unwanted contact between conductive materials and the substrate.
Implementation Method 1
implementing an etch-stop at the bottom of the source and/or drain epitaxy and over a buried power rail (BPR) within the CFET structure
Implementation Method 2
using blocking materials and insulating layers to prevent contact between conductive materials and the silicon substrate
Data Source
AI summary
A method of forming a complementary field effect transistor (CFET) is provided. The method includes adding a blocking material to a vertical channel of the CFET having an epitaxial growth, the blocking material being located below and in contact with a lower portion of the growth, adding an insulating material to an open area within the vertical channel to surround a portion of the epitaxial growth, performing an etch to (i) remove a portion of the insulating material, (ii) expose a contact surface of the epitaxial growth and (iii) provide a vertical opening within the vertical channel, the etch leaving a portion of the blocking material, and filling in the vertical opening with a conductive material, the conductive material reaching the exposed contact surface of the epitaxial growth, the blocking material remaining below the conductive material to prevent contact between the conductive material and a silicon substrate below the growth.