Nanosheet Gate Structure With Separation Layers for Parasitic Control
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Solution Overview
Problem
The increasing integration of field effect transistors in integrated circuit devices leads to issues with contact resistance and parasitic capacitance, affecting performance and reliability.
Innovation Solution
The integration of a fin-type active structure with a nanosheet stack, a gate structure, and a source/drain structure, including a silicide and silicon separation layer, along with a bottom dielectric isolation, to reduce contact resistance and parasitic capacitance, with the source/drain structure made of metal to enhance conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of integrated circuit devices decreases to increase the degree of integration, then more field effect transistors can be integrated on a substrate, but contact resistance between elements and parasitic capacitance increase, affecting integrated circuit performance
Solution Approach 1:
The patent transitions from planar 2D transistor layouts to a 3D vertical architecture where nanosheets are stacked vertically above a fin-type active structure. This dimensional change allows multiple transistor channels to occupy the same footprint area, significantly increasing integration density while maintaining electrical performance through controlled vertical spacing and gate wrapping.
Solution Approach 2:
The gate structure completely surrounds each nanosheet channel in a wrap-around configuration, with the gate electrode enveloping the nanosheet from all sides. This nested arrangement provides superior electrostatic control over the channel, reducing parasitic effects and improving carrier modulation while maintaining compact integration.
2Area of moving object
If horizontal nanosheets are stacked on the same layout area to increase integration, then the size of integrated circuit elements is reduced, but contact resistance and parasitic capacitance are generated, affecting integrated circuit performance
Solution Approach 1:
Silicide separation layers are strategically positioned between adjacent nanosheets and at interfaces with source/drain regions. These intermediary layers serve multiple functions: they reduce parasitic capacitance by providing electrical isolation, minimize contact resistance at critical interfaces, and prevent unwanted electrical coupling between stacked nanosheets while maintaining compact vertical integration.
Solution Approach 2:
The patent applies different materials and structures to specific locations within the device. Silicide layers are placed only where needed for contact optimization and parasitic reduction, while the gate structure provides localized electrostatic control around each nanosheet. This localized application of different structures optimizes performance without unnecessarily increasing overall device complexity or size.
Data Source
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Figure 2B
AI summary
An integrated circuit device may include a fin-type active structure (F1) elongated in a first horizontal direction (X), a nanosheet stack (NSS) including nanosheets on the fin-type active structure, a gate structure (160) extending between the nanosheets, a source/drain structure (130) on the fin-type active structure at a position adjacent to the gate structure and facing the nanosheet stack in the first horizontal direction, a vertical separation layer (150) including a silicon layer (151A) in contact with a silicide separation layer (151B). The silicide separation layer is between the source/drain structure and each of the nanosheet stack and the gate structure. The silicon separation layer is between the silicide separation layer and each of the nanosheet stack and the gate structure. The source/drain structure includes a metal. The gate structure includes at least one sub-gate (160S) surrounding at least one nanosheet among the plurality of nanosheets on the fin-type active structure. A bottom dielectric isolation (BDI) is under the lower surface of the gate structure.