Curved Heteroepitaxial Interfaces for Low-Defect FinFET Source/Drain
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing stress-induced defects and impurity defects at heterogeneous epitaxial interfaces in FETs due to lattice mismatch and atomic migration during high-temperature epitaxial growth processes, which affect device performance and manufacturing complexity.
Innovation Solution
The method involves selectively modifying the surfaces of channel regions and substrates to create curved interface profiles and applying passivation layers to reduce interfacial stress and atomic migration, thereby minimizing defects and impurity concentrations at epitaxial interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature epitaxial growth processes are used to form semiconductor structures, then device performance can be improved through controlled material deposition, but stress-induced defects and impurity defects increase due to lattice mismatch and atomic migration at heterogeneous epitaxial interfaces
Solution Approach 1:
The patent applies preliminary action by performing surface modification on the channel region and substrate surfaces before epitaxial growth. This pre-treatment creates curved interface profiles that anticipate and prevent stress concentration during subsequent high-temperature epitaxial processes, thereby reducing stress-induced defects while maintaining device performance
Solution Approach 2:
The patent implements curvature by modifying surfaces to create curved interface profiles at epitaxial interfaces. This curvature distributes stress more evenly across the interface compared to flat interfaces, reducing stress concentration and preventing defect formation during thermal epitaxial growth processes
2Ease of manufacture
If conventional flat interface profiles are used in epitaxial structures, then manufacturing processes are simpler, but interfacial stress increases leading to higher defect concentrations
Solution Approach 1:
The patent modifies conventional flat interface profiles to curved profiles through surface modification processes. This curvature reduces interfacial stress by distributing mechanical loads more evenly across the epitaxial interface, thereby reducing defect formation while maintaining manufacturing feasibility
3Manufacturing precision
If surface modification and passivation layers are applied to reduce interfacial stress, then defect concentrations decrease by 50% to 90%, but manufacturing process complexity increases
Solution Approach 1:
The patent performs surface modification as a preliminary step before epitaxial growth, preparing surfaces in advance to achieve the desired curved interface profiles. This approach consolidates multiple functions into a pre-treatment step, reducing the need for additional corrective processes later and managing overall process complexity
Solution Approach 2:
The patent introduces passivation layers as intermediary structures between the channel region and epitaxial layers. These passivation layers serve as mediators that reduce atomic migration and protect the interface during high-temperature processes, achieving defect reduction while managing process complexity through a dedicated protective layer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces interfacial stress by 50% to 80% and impurity concentrations by 50% to 90%, improving the performance and manufacturing efficiency of semiconductor devices by minimizing defects at heterogeneous epitaxial interfaces.
Implementation Method 1
applying passivation layers to reduce interfacial stress and atomic migration
Implementation Method 2
modifying surfaces to curved profiles to reduce interfacial stress
Data Source
AI summary
A method for reducing stress induced defects in heterogeneous epitaxial interfaces of a semiconductor device is disclosed. The method includes forming a fin structure with a fin base, a superlattice structure on the fin base, forming a polysilicon gate structure on the fin structure, forming a source/drain (S/D) opening within a portion of the fin structure uncovered by the polysilicon gate structure, modifying the first surfaces of the first layers to curve a profile of the first surfaces, depositing first, second, and third passivation layers on the first, second, and third surfaces, respectively, forming an epitaxial S/D region within the S/D opening, and replacing the polysilicon gate structure with a metal gate structure. The superlattice structure includes first and second layers with first and second lattice constants, respectively, and the first and second lattice constants are different from each other.