Gate Dielectric Thickness Control in FinFET and GAA Trenches
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Solution Overview
Problem
The challenge in the semiconductor industry is to form reliable semiconductor devices at increasingly smaller sizes, as feature sizes decrease, making fabrication processes more complex and difficult.
Innovation Solution
The solution involves forming semiconductor device structures with FinFETs and gate all around (GAA) transistor structures using advanced patterning methods like double-patterning or multi-patterning processes, and employing atomic layer deposition (ALD) to create gate dielectric layers with varying thicknesses in different trenches, allowing for improved transistor performance by adjusting chemisorption forces of ALD precursors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then production efficiency is improved and costs are lowered, but fabrication process complexity increases and manufacturing difficulty increases
Solution Approach 1:
The fabrication process is divided into multiple discrete stages including forming first and second trenches at different depths, selective epitaxial growth in specific regions, and staged doping processes. This segmentation allows complex device structures to be built through manageable sequential steps rather than attempting to create all features simultaneously, thereby reducing overall process complexity while maintaining high functional density
Solution Approach 2:
The method performs preliminary actions by first forming the deeper first trench and performing initial doping before forming the shallower second trench. This preliminary structuring creates a foundation that simplifies subsequent processing steps, as later operations can build upon pre-established features rather than creating everything from scratch, thus improving productivity while managing complexity
2Productivity
If feature sizes are decreased to increase functional density, then more devices per chip area are achieved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by forming trenches and performing epitaxial growth in specifically defined regions with precise depth control. Different areas of the semiconductor substrate receive different treatments - for example, first trenches are formed to a greater depth in certain regions while second trenches are formed to a lesser depth in other regions. This localized precision allows high functional density to be achieved without requiring uniform ultra-precise manufacturing across the entire chip, as each region is optimized for its specific function
Solution Approach 2:
The method transitions from two-dimensional planar processing to three-dimensional vertical structuring by forming trenches at different depths and performing selective epitaxial growth. This dimensional change allows multiple device features to be stacked vertically, increasing functional density without proportionally increasing the lateral precision requirements, thereby achieving higher device counts per chip area while managing manufacturing precision constraints
3Reliability
If gate dielectric layer thickness is varied in different trenches to optimize transistor performance, then short channel transistors achieve improved driving current and switching speed, but process complexity increases
Solution Approach 1:
The patent implements local quality by depositing gate dielectric material to different thicknesses in different trenches through selective deposition processes. Short channel transistors receive thinner gate dielectric layers to enable higher driving current and faster switching, while long channel transistors receive thicker gate dielectric layers to withstand higher voltages. This localized differentiation optimizes transistor performance for each specific application without requiring complete process redesign, as the variation is achieved through targeted deposition parameters in different spatial locations
Solution Approach 2:
The method employs parameter changes by varying the gate dielectric layer thickness parameter across different device regions. By controlling deposition conditions such as deposition rate, duration, and precursor delivery to specific trenches, the patent achieves different dielectric thicknesses that directly affect transistor electrical characteristics. This parameter variation allows optimization of driving current and switching speed for short channel devices while maintaining voltage withstand capability for long channel devices, thereby improving overall transistor performance without fundamentally changing the process architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of semiconductor devices with improved performance, including enhanced driving current, reduced leakage current, and increased switching speed for short channel transistors, while allowing long channel transistors to withstand high voltages, thus addressing the complexity of smaller feature sizes.
Implementation Method 1
adjusting chemisorption forces of ALD precursors
Data Source
AI summary
A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The method includes depositing a gate dielectric layer over the insulating layer and in the wide trench and the narrow trench using an atomic layer deposition process. The method includes forming a gate electrode layer over the gate dielectric layer. The method includes removing the gate dielectric layer and the gate electrode layer outside of the wide trench and the narrow trench.