Dual Metal Gate Nanoribbon Stack With Sacrificial Plug Etching
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Solution Overview
Problem
The integration of N-type and P-type transistors within a single stack in gate-all-around (GAA) semiconductor devices is challenging due to difficulties in removing the first workfunction metal from between nanoribbon channels without affecting the bottom transistors, leading to increased spacing and fin height issues, which complicates shallow trench isolation and polysilicon processing.
Innovation Solution
The use of a sacrificial plug material between the semiconductor channels of the top transistor allows for reduced etching time and spacing between nanoribbon channels, enabling the deposition of dual workfunction metals with spacings as low as 20 nm or less, facilitating optimal device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the first workfunction metal is etched away from the top nanoribbon channels to enable dual metal gate, then the top transistor can use a different workfunction metal, but the etching process cannot be performed without affecting the first workfunction metal around the bottom transistors, leading to increased spacing between channels
Solution Approach 1:
The patent divides the etching process into two distinct stages: first etching the workfunction metal from the top channels while protecting bottom channels, then etching from the bottom. This segmentation allows selective removal of workfunction metal from specific transistor regions without affecting others, enabling dual metal gate integration with reduced spacing.
Solution Approach 2:
The patent performs preliminary actions by depositing sacrificial materials (such as silicon nitride or silicon oxide) on the bottom channels before the first etching step. These sacrificial layers protect the bottom workfunction metal during the top channel etching process, enabling subsequent dual metal gate formation without compromising bottom transistor integrity.
2Length of stationary object
If the spacing between top and bottom nanoribbon channels is reduced to decrease fin height, then shallow trench isolation and polysilicon processing become more difficult, but larger spacing is needed to remove first workfunction metal without affecting bottom transistors
Solution Approach 1:
Sacrificial materials are deposited on bottom channels before workfunction metal removal, creating a protective barrier that enables close spacing while maintaining manufacturing feasibility. This preliminary protection allows the etching process to proceed without damaging bottom transistors even when channels are closely spaced.
Solution Approach 2:
Sacrificial materials act as intermediary protective layers between the etching process and the bottom workfunction metal. These intermediary layers enable the etching to proceed aggressively enough to remove top workfunction metal completely, while the sacrificial material absorbs the etching impact and protects the bottom channels.
3Manufacturing precision
If etching time is extended to completely remove first workfunction metal from top channels, then dual metal gate is achieved, but the first workfunction metal around bottom transistors is also removed
Solution Approach 1:
The etching process is segmented into multiple selective steps with different target regions. The first etching step targets only top channels with protective coverage on bottom channels, and the second etching step removes any remaining workfunction metal from top channels. This segmentation achieves complete removal from top channels while preserving bottom channel workfunction metal.
Solution Approach 2:
Sacrificial protective layers are applied to bottom channels before the etching process begins. This preliminary protection allows the etching to proceed for the duration needed to completely remove workfunction metal from top channels without compromising the integrity of bottom transistor workfunction metal.
Data Source
AI summary
Embodiments disclosed herein include semiconductor devices and methods of making such devices. In an embodiment, the semiconductor device comprises a plurality of stacked semiconductor channels comprising first semiconductor channels and second semiconductor channels over the first semiconductor channels. In an embodiment a spacing is between the first semiconductor channels and the second semiconductor channels. The semiconductor device further comprises a gate dielectric surrounding individual ones of the semiconductor channels of the plurality of stacked semiconductor channels. In an embodiment, a first workfunction metal surrounds the first semiconductor channels, and a second workfunction metal surrounds the second semiconductor channels.