Buried Low-k Dielectric Etch Stop for Source-Drain Gate Contacts
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Solution Overview
Problem
Chemical etching in semiconductor manufacturing often results in excessive material removal and unwanted open circuits in integrated circuit devices due to the lack of precise control over the etching process, particularly in the connections between source/drain and gate components.
Innovation Solution
The use of a low-k dielectric material with high etch selectivity to silicon nitride, acting as an etch stop layer, and a nitride cap material to protect underlying layers during the etching process, ensuring precise material removal and preventing damage to sensitive components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical etching is used to create patterns in semiconductor manufacturing, then material removal is achieved, but excessive material removal occurs causing unwanted open circuits
Solution Approach 1:
An etch stop layer comprising silicon nitride is formed prior to the chemical etching process. This layer is deposited in advance to precisely control where etching should terminate, preventing the chemical etchant from removing excessive material and creating open circuits in the source/drain to gate connection regions.
Solution Approach 2:
The silicon nitride etch stop layer acts as an intermediary between the chemical etchant and the underlying sensitive components. It selectively resists the etching solution, allowing precise material removal in desired areas while protecting critical regions from unwanted etching that would cause open circuits.
2Ease of manufacture
If chemical etching removes material to create desired patterns, then pattern formation is achieved, but unwanted open circuits are introduced
Solution Approach 1:
The etch stop layer is deposited beforehand in specific locations where material removal should be prevented. This preliminary action enables the chemical etching process to easily form patterns in exposed areas while the etch stop layer pre-defines the boundaries, ensuring precise control over material removal and preventing open circuits.
Solution Approach 2:
The etch stop layer is applied selectively to specific regions rather than uniformly across the entire substrate. This local application allows chemical etching to proceed freely in areas where pattern formation is desired while providing localized protection in areas where material removal would cause open circuits.
3Shape
If etching solution penetrates to remove underlying material, then desired shape is created, but excessive material removal occurs
Solution Approach 1:
The etch stop layer is formed in advance at predetermined locations to serve as a barrier. When the chemical etching solution penetrates to create the desired shape, this pre-formed layer stops the etching process at the correct depth, preventing excessive material removal and ensuring the quantity of material removed matches the design requirements.
Solution Approach 2:
The etch stop layer acts as an intermediary barrier between the chemical etchant and the underlying material. It allows the etching solution to remove material to the desired shape while mediating the etching process to prevent penetration beyond the required depth, thus controlling the total quantity of material removed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance and minimizes the formation of open circuits by protecting critical layers from unwanted etching, thereby enhancing the reliability and performance of integrated circuit devices.
Implementation Method 1
a low-k dielectric material with high etch selectivity to silicon nitride, acting as an etch stop layer
Implementation Method 2
a nitride cap material to protect underlying layers during the etching process
Data Source
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AI summary
An apparatus comprising a source or drain of a field effect transistor (FET), a first dielectric between a portion of the source or drain and a FET gate, the first dielectric comprising silicon nitride, and a second dielectric above at least a portion of the first dielectric, the second dielectric comprising silicon oxide doped with at least one of oxygen or carbon, the second dielectric having a dielectric constant lower than the first dielectric.