Multi-Gate Transistor Channel Shaping for Lower Junction Resistance
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Solution Overview
Problem
Existing multi-gate devices, such as MBC transistors, face challenges with increased parasitic resistance and junction resistance due to the formation of inner spacer features, leading to reduced on-state current and increased threshold voltage, as the scaling down process results in etching of channel layers and reduced junction overlap areas.
Innovation Solution
The method involves forming a stack with channel layers thicker than sacrificial layers, selectively removing sacrificial layers to release channel members, and trimming them to increase channel-channel spacing, while forming wider inner spacers along the gate length direction to prevent damage to source/drain features, resulting in a dog-bone shape of channel members with an enlarged junction overlap area, thereby reducing junction resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional inner spacer features are formed by recessing sacrificial layers, then gate structure spacing is achieved, but junction overlap region is reduced leading to increased parasitic resistance
Solution Approach 1:
The patent performs preliminary trimming of channel layers to a dog-bone shape before forming inner spacers. This preliminary action creates additional space that allows inner spacers to be formed without encroaching on the junction overlap region, thereby maintaining both gate spacing and junction overlap integrity
Solution Approach 2:
The patent segments the channel layer into different thickness regions - a thicker middle section and thinner end sections - creating the dog-bone shape. This segmentation allows the inner spacer to be positioned in the thinner end region without reducing the junction overlap in the thicker middle region
2Productivity
If feature dimensions are scaled down, then production efficiency is improved, but parasitic resistance and threshold voltage increase
Solution Approach 1:
The patent applies local quality by creating non-uniform channel layer thickness - thicker at the ends for junction overlap and thinner in the middle for gate spacing. This local variation in thickness allows the structure to maintain electrical performance at scaled dimensions while preserving sufficient junction overlap region
Solution Approach 2:
The patent introduces a vertical thickness dimension variation within the horizontal channel layer, creating the dog-bone shape with varying thickness along its length. This adds a dimensional degree of freedom that allows simultaneous optimization of junction overlap area and gate spacing at scaled dimensions
3Strength
If inner spacer features are formed, then gate structure integrity is improved, but on-state resistance increases due to reduced junction overlap
Solution Approach 1:
The patent performs preliminary trimming of channel layers to a dog-bone shape before forming inner spacers. This preliminary action creates additional space that allows inner spacers to be formed without encroaching on the junction overlap region, thereby maintaining both gate spacing and junction overlap integrity
Solution Approach 2:
The patent segments the channel layer into different thickness regions - a thicker middle section and thinner end sections - creating the dog-bone shape. This segmentation allows the inner spacer to be positioned in the thinner end region without reducing the junction overlap in the thicker middle region
Data Source
AI summary
A semiconductor device includes a substrate, two source/drain features disposed on the substrate, a stack of channel layers disposed over the substrate and between the two source/drain features, and a gate structure disposed over and wrapping around the stack of channel layers. Each channel layer of the stack of channel layers has a dog-bone shape in a cross-sectional view including the two source/drain features and the stack of channel layers. The gate structure includes a seam.