Silicon Superlattice Structure for Carrier Mobility and Diffusion Control
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Solution Overview
Problem
Current semiconductor devices do not fully leverage advanced semiconductor materials and processing techniques to achieve optimal performance, particularly in enhancing charge carrier mobility and reducing defects.
Innovation Solution
The formation of a superlattice structure with a plurality of stacked silicon monolayers and non-semiconductor monolayers within the crystal lattice, which reduces the effective mass of charge carriers and enhances mobility, while also acting as a barrier to prevent dopant and material diffusion, thereby improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional semiconductor materials and processing techniques are used, then manufacturing simplicity is maintained, but charge carrier mobility is insufficient and device performance is limited
Solution Approach 1:
The semiconductor structure is segmented into multiple thin layers (first semiconductor layer, superlattice layer, second semiconductor layer) with distinct functions. The superlattice itself is segmented into repeating units of semiconductor and non-semiconductor monolayers, creating a structured complexity that enables enhanced charge carrier mobility through quantum confinement effects while maintaining manufacturability through systematic layering
Solution Approach 2:
The invention employs composite material structures by combining semiconductor layers with non-semiconductor layers in a superlattice configuration. This composite approach allows the semiconductor regions to provide charge transport while the non-semiconductor regions provide structural support and diffusion barriers, achieving superior mobility without sacrificing material stability
2Reliability
If dopant diffusion is allowed to occur naturally, then manufacturing process simplicity is maintained, but device performance degrades due to unwanted dopant distribution
Solution Approach 1:
Non-semiconductor layers are introduced as intermediary barriers between semiconductor regions. These intermediary layers act as diffusion barriers that prevent unwanted dopant transport while allowing the overall structure to maintain simple manufacturing processes. The intermediaries enable precise dopant distribution control without requiring complex process sequencing
Solution Approach 2:
The superlattice structure with embedded non-semiconductor layers is formed preliminarily before final dopant introduction. This preliminary structural preparation creates built-in diffusion barriers that pre-establish controlled dopant distribution pathways, eliminating the need for complex subsequent process steps to achieve proper dopant placement
3Speed
If advanced superlattice structures are implemented, then charge carrier mobility is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The invention utilizes parameter changes at the monolayer scale, where each layer is precisely controlled in thickness (single monolayer precision). By changing the thickness parameters of individual semiconductor and non-semiconductor layers, the superlattice achieves quantum confinement effects that enhance charge carrier mobility while the systematic nature of the layering allows standard manufacturing techniques to achieve the required precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The superlattice structure achieves higher charge carrier mobility and reduces defects, leading to improved semiconductor device performance and the ability to form high-K dielectrics that enhance device mobility and reduce scattering effects.
Implementation Method 1
The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions
Implementation Method 2
forming a superlattice above the first single crystal silicon layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions
Data Source
AI summary
A method for making a semiconductor device may include forming a first single crystal silicon layer having a first percentage of silicon 28, and forming a superlattice above the first single crystal silicon layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The method may further include forming a second single crystal silicon layer above the superlattice having a second percentage of silicon 28 higher than the first percentage of silicon 28.