Nested TCG-GAA Gate Structures for Multi-Vt MOSFET Scaling
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (finFETs) to achieve higher storage capacity, faster processing, and lower costs, particularly in forming gate structures that allow for multiple threshold voltages on the same substrate, which is constrained by the geometry of the FET gate structures and becomes increasingly difficult with continuous scaling.
Innovation Solution
The implementation of through-channel gate (TCG) structures and gate-all-around (GAA) structures between source/drain regions, where TCG structures extend through nanostructured channel regions and are surrounded by GAA structures, utilizing negative capacitance gate dielectric layers to prevent parasitic capacitance and allow for modulation of threshold voltage by controlling applied voltages, enabling multi-Vt functionality and reducing leakage current and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional gate structures are used in scaled-down semiconductor devices, then manufacturing complexity increases, but the ability to achieve multiple threshold voltages on the same substrate deteriorates
Solution Approach 1:
The gate structure is segmented into multiple independent gates (first gate structure and second gate structure) that can be independently controlled. Each gate can apply different voltages to different regions of the channel, enabling multiple threshold voltages on the same substrate. The segmentation allows each gate to function semi-independently, resolving the contradiction by dividing the gate into controllable segments rather than using a single conventional gate.
Solution Approach 2:
The patent transitions from planar gate structures to vertically stacked three-dimensional gate structures. The first and second gate structures are positioned at different vertical levels, with the second gate surrounding portions of the first gate. This dimensional change enables independent voltage control along different spatial dimensions, achieving multi-threshold voltage capability without increasing lateral complexity.
2Productivity
If device dimensions are continuously scaled down to increase storage capacity and processing speed, then manufacturing complexity increases, but the formation of gate structures with multiple threshold voltages becomes increasingly difficult
Solution Approach 1:
The second gate structure is nested around portions of the first gate structure, creating a concentric, multi-layered configuration. This nesting approach allows both gates to be formed in a self-aligned manner, reducing the need for additional lithography steps and alignment processes. The nested geometry simplifies fabrication by enabling sequential formation where the outer gate is deposited around the already-formed inner gate, making the process more manufacturable despite continuous scaling.
Solution Approach 2:
The patent utilizes changes in material parameters, specifically employing different dielectric materials with different dielectric constants (k-values) for the first and second gate dielectric layers. This allows independent threshold voltage control through material parameter selection rather than relying solely on geometric scaling. By changing dielectric parameters, the invention achieves multi-Vt functionality without requiring increasingly complex geometric configurations as devices scale down.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the achievement of multiple threshold voltages in a single FET, reducing power consumption and device area, while also minimizing the number of FETs required in an integrated circuit, thereby improving device performance and reducing manufacturing costs.
Implementation Method 1
utilizing negative capacitance gate dielectric layers to prevent parasitic capacitance and allow for modulation of threshold voltage by controlling applied voltages
Data Source
AI summary
A semiconductor device with different configurations of gate structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a stack of nanostructured channel regions disposed on a fin structure, a first gate structure disposed within the stack of nanostructured channel regions, a second gate structure surrounds the first gate structure about a first axis and surrounds the nanostructured channel regions about a second axis different from the first axis, and first and second contact structures disposed on the first and second gate structures, respectively.