Surface-Treated Semiconductor Contact With 2D Layer Schottky Barrier Control
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Solution Overview
Problem
The existing methods for reducing contact resistivity between semiconductor and metal layers are limited by the phenomenon of work function pinning, which restricts the lowering of the Schottky energy barrier regardless of the metal layer used.
Innovation Solution
A semiconductor device with a surface-treated semiconductor layer using a material with an electron affinity of 4 eV or greater, combined with a two-dimensional (2D) material layer, which forms a van der Waals bond and creates a surface dipole exceeding 1.2 (a.u.), thereby reducing the Schottky energy barrier to 0.3 eV or less.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal layer with specific work function is used to reduce Schottky energy barrier, then contact resistivity is reduced, but work function pinning occurs on semiconductor layer surface limiting further reduction
Solution Approach 1:
The semiconductor layer surface is pre-treated with surface-treating elements (such as oxygen, nitrogen, or carbon-containing groups) before metal layer formation. This preliminary surface modification creates a controlled surface dipole that adjusts the Schottky energy barrier before the metal layer is deposited, preventing work function pinning from limiting the contact resistivity reduction.
Solution Approach 2:
The surface dipole moment of the semiconductor layer is actively modified by introducing surface-treating elements with different electronegativities and bonding configurations. By changing the surface chemical composition and structure, the Schottky energy barrier is tuned to achieve optimal contact resistivity values that would be impossible with metal work function selection alone.
2Reliability
If surface treatment is applied to semiconductor layer to reduce Schottky energy barrier, then contact resistivity decreases, but semiconductor layer intrinsic nature must be preserved
Solution Approach 1:
Surface treatment is applied only to the outermost surface region of the semiconductor layer, creating a localized modification layer. The surface-treating elements are confined to the surface region and do not diffuse deeply into the bulk semiconductor, thereby maintaining the intrinsic properties and crystal structure of the semiconductor layer while achieving the desired electrical contact characteristics.
Solution Approach 2:
The surface treatment is performed as a preliminary step before metal layer deposition and device operation. This timing ensures that the surface modification is established before any subsequent processing that might cause unwanted diffusion or contamination, preserving the semiconductor's bulk properties while achieving surface-level electrical optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively lowers contact resistivity by increasing the surface dipole of the semiconductor layer, retaining its intrinsic nature while reducing the Schottky energy barrier, thus improving the electrical characteristics of the semiconductor device.
Implementation Method 1
the surface-treating element may form a surface dipole with the element of the semiconductor layer
Implementation Method 2
the surface-treating element may be covalently bonded with an element contained in the semiconductor layer
Implementation Method 3
the 2D material layer may cause the surface-treating element to be pinned on a surface of the semiconductor layer through a van der Waals bond
Data Source
AI summary
Disclosed is a semiconductor device including a surface-treated semiconductor layer. The semiconductor device includes a metal layer, a semiconductor layer electrically contacting the metal layer and having a surface treated with an element having an electron affinity of about 4 eV or greater, and a two-dimensional (2D) material layer disposed between the metal layer and the semiconductor layer and having a 2D crystal structure.