Gate Cut Isolation Using Dummy Fins for Dense Fin Layouts
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Solution Overview
Problem
Conventional methods for forming gate cut features in semiconductor fabrication face challenges in spacing and alignment due to rigid constraints, limiting the ability to design complex patterns and increase pattern density in field-effect transistors like GAA and FinFET devices.
Innovation Solution
The introduction of dielectric dummy fin structures between functional fin structures allows for the deposition of a gate layer, which is then etched to expose top surfaces of the dummy fin structures, enabling the placement of a conductive layer to electrically connect gate segments and the formation of cut features over dummy fin structures to isolate adjacent gate segments, thereby relaxing spacing constraints and enabling closer fin structure spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication methods are used for cut gate structures, then alignment and overlay constraints are maintained, but spacing requirements between fin structures increase, reducing pattern density
Solution Approach 1:
A dielectric layer is introduced as an intermediary between the fin structures and the gate structure. This dielectric layer extends over the fin structures and is etched to form recesses that receive the gate structure. The dielectric layer acts as a mediator that allows the gate to be positioned precisely without direct contact requirements with the fin structures, thereby relaxing spacing constraints while maintaining alignment precision.
Solution Approach 2:
The invention transitions from a planar gate structure to a three-dimensional gate structure by forming the gate within recesses of the dielectric layer. This dimensional change allows the gate to be positioned at a different vertical level relative to the fin structures, enabling closer horizontal spacing while maintaining proper electrical connection and alignment through the vertical dimension.
2Area of stationary object
If fin structures are spaced closer together to increase pattern density, then area utilization improves, but alignment and overlay constraints for cut gate structures become more difficult to satisfy
Solution Approach 1:
The dielectric layer serves as a buffer and alignment reference that decouples the positioning requirements between fin structures and gate structures. By forming the gate within recesses of this intermediary layer, the alignment precision requirement is maintained through the recess geometry while allowing closer spacing between fin structures to increase pattern density.
Solution Approach 2:
The gate structure is segmented into discrete units, each formed within its own recess in the dielectric layer. This segmentation allows each gate to be independently positioned and formed, enabling closer spacing between fin structures while maintaining precise alignment through the recess structure rather than requiring continuous gate alignment across multiple fins.
3Ease of manufacture
If conventional gate structures are used, then fabrication process simplicity is maintained, but spacing requirements increase, limiting circuit density
Solution Approach 1:
The dielectric layer formation and gate structure formation processes are merged into a integrated sequence. The dielectric layer is deposited to extend over the fin structures, then etched to form recesses, and the gate structure is formed within these recesses. This merging of steps creates a unified process flow that achieves closer spacing requirements while maintaining fabrication simplicity through process integration rather than adding separate complex steps.
Data Source
AI summary
A semiconductor structure includes a plurality of fin structures extending along a first direction, a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures. The semiconductor structure further includes a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments, and a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures.