3D Vertical Transistor Stack With Epitaxial Shell Mobility Gain
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in scaling transistors beyond single-digit nanometer nodes, as traditional two-dimensional (2D) circuits reach limitations, and there is a need for three-dimensional (3D) semiconductor circuits where transistors are stacked vertically to increase density and performance.
Innovation Solution
The method involves forming a substrate with a layer stack of semiconductor channel layers separated by an intermediate layer, creating core channel structures with vertical conductive paths, and growing epitaxial shells around these structures to form vertically stacked transistors, allowing for customizable conductivity types and increased density without thickness constraints, using techniques like epitaxial growth and wafer bonding for 3D integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional two-dimensional (2D) circuits are used for scaling, then manufacturing processes remain simple, but transistor density and performance are limited at single-digit nanometer nodes
Solution Approach 1:
The patent transitions from traditional two-dimensional planar transistors to three-dimensional vertically stacked transistors. Multiple transistor channels are stacked vertically on top of each other, enabling increased transistor density without increasing the footprint area. This dimensional change allows continued scaling at single-digit nanometer nodes by utilizing the vertical space above the substrate.
2Productivity
If vertically stacked transistors are implemented, then transistor density increases, but manufacturing precision requirements increase
Solution Approach 1:
The vertical channel is segmented into multiple discrete transistor channels separated by intermediate layers. Each channel can be independently formed and controlled, allowing for modular manufacturing. The intermediate layers act as separation structures that define the boundaries between adjacent transistor channels, simplifying the alignment process compared to forming a continuous vertical structure.
3Reliability
If epitaxial shells are grown around core channel structures, then transistor performance and mobility are improved, but manufacturing process complexity increases
Solution Approach 1:
The core channel structures are formed first as templates before growing the epitaxial shells. This preliminary formation of the core structure provides a defined geometry and material foundation that guides the subsequent epitaxial growth process. The core channels are formed using standard semiconductor fabrication techniques, and then the epitaxial shells are grown around them in a controlled manner to achieve the desired transistor performance characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher transistor density with improved mobility and reduced costs, achieving 3D integration with 360-degree rotational symmetry and robust diffusion breaks, suitable for both CMOS and CFET designs, enhancing performance and scalability beyond traditional 2D limitations.
Implementation Method 1
forming a first epitaxial shell around the first core channel structure
Data Source
AI summary
A microfabricated transistor device includes a vertical stack of two or more channels of field effect transistors on a semiconductor substrate. Each of the channels has a vertical conductive path relative to a surface of the semiconductor substrate. At least one of the channels includes a shell formed around a core material, the shell including epitaxial material. The vertical stack can include a channel for a PMOS field effect transistor, and a channel for an NMOS field effect transistor.