Dual-Layer Inner Spacer Structure for Low-Capacitance Multi-Gate Transistors
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Solution Overview
Problem
Conventional inner spacer features in multi-bridge-channel transistors face challenges in balancing etch resistance and low dielectric constant, leading to potential damage during sacrificial layer removal and increased parasitic capacitance due to high dielectric constant materials.
Innovation Solution
The implementation of inner spacer features comprising an outer layer with a higher dielectric constant and an inner layer with a lower dielectric constant, made of silicon, carbon, oxygen, and nitrogen, where the outer layer is etched away to reduce parasitic capacitance and prevent source/drain feature damage during channel release.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional inner spacer features are made with etch resistant dielectric material, then etch resistance is improved, but dielectric constant increases leading to increased parasitic capacitance
Solution Approach 1:
The inner spacer feature is divided into two distinct layers: a first inner spacer layer with high etch resistance and a second inner spacer layer with low dielectric constant. This segmentation allows each layer to perform its specialized function independently, resolving the contradiction between needing etch resistance and minimizing parasitic capacitance.
Solution Approach 2:
Different regions of the inner spacer feature are assigned different material properties: the first layer (closer to the sacrificial layer) has high etch resistance to protect during removal, while the second layer (closer to the source/drain) has low dielectric constant to minimize capacitance. This local differentiation of properties resolves the global contradiction.
2Reliability
If inner spacer feature thickness is increased to prevent source/drain damage, then protection is improved, but parasitic capacitance increases
Solution Approach 1:
The thickness is segmented into two functional layers: the first layer provides the necessary protection during etching with appropriate thickness, while the second layer is kept thin to minimize capacitance contribution. This segmentation allows optimization of each layer's thickness for its specific purpose.
Solution Approach 2:
The dielectric constant parameter is changed between layers: the first layer uses high-k material for protection, while the second layer uses low-k material to reduce capacitance. This parameter differentiation allows simultaneous achievement of protection and low capacitance.
Data Source
AI summary
A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. The channel member further includes a first ridge on a top surface of the channel member and disposed at an interface between the channel portion and the first connection portion. The first ridge partially extends between the first inner spacer feature and the gate structure.