GAA Nanosheet Gate Stack With Nitrogen-Rich TiN Work Function Layer
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Solution Overview
Problem
The challenge in fabricating horizontal gate-all-around (HGAA) transistors is the unsatisfactory nanosheet formation using current methods, particularly with a single epitaxial process, which leads to compromised gate control and increased short-channel effects due to scaling down of gate lengths, affecting transistor performance.
Innovation Solution
A method for manufacturing gate-all-around (GAA) FET devices involves forming a stack of alternating semiconductor layers over a substrate, patterning fin structures, embedding them in an insulating material, forming gate spacers, and selectively removing sacrificial layers to create nanosheets, followed by depositing a nitrogen-rich titanium nitride work function layer using plasma-enhanced atomic layer deposition (PEALD) to improve gate control and reduce threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If gate length is scaled down to increase drive current, then transistor performance improves, but short-channel effects worsen
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional gate-all-around structures that wrap around the channel in multiple dimensions. This dimensional change provides superior gate control over the channel region, enabling effective suppression of short-channel effects even at scaled-down gate lengths while maintaining high drive current capability
Solution Approach 2:
The patent employs composite material structures including stacked semiconductor layers with different compositions (e.g., Si/SiGe), high-k dielectric materials, and metal gate combinations. These composite structures enable simultaneous optimization of gate control, threshold voltage adjustment, and drive current characteristics in scaled transistors
2Ease of manufacture
If single epitaxial process is used for nanosheet formation, then manufacturing simplicity is maintained, but nanosheet formation quality deteriorates
Solution Approach 1:
The patent divides the nanosheet formation process into multiple sequential epitaxial growth stages, each creating specific semiconductor layers with controlled compositions and thicknesses. This segmented approach enables precise control over nanosheet properties while maintaining compatibility with standard CMOS manufacturing processes
Solution Approach 2:
The patent utilizes parameter changes during epitaxial growth, including temperature variations, pressure adjustments, and gas flow control, to achieve different material compositions and crystal structures in successive layers. These parameter modifications enable high-quality nanosheet formation with precise thickness and composition control
3Reliability
If nitrogen-rich titanium nitride work function layer is deposited at lower temperatures, then gate control improves and threshold voltage decreases, but deposition process complexity increases
Solution Approach 1:
The patent employs parameter changes in the deposition process, specifically using plasma-enhanced atomic layer deposition (PEALD) with controlled nitrogen incorporation at reduced temperatures. By adjusting deposition temperature, plasma power, and precursor flow rates, the process achieves nitrogen-rich titanium nitride layers with optimized work function and threshold voltage characteristics
Solution Approach 2:
The patent creates a composite gate stack structure consisting of multiple layers including high-k dielectric, titanium nitride work function layer, and metal gate materials. This composite structure enables simultaneous achievement of strong gate control, appropriate threshold voltage, and thermal compatibility through the combined properties of different materials
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances gate control, reduces short-channel effects, and adjusts the driving current of GAA FET devices, improving transistor performance by forming high-quality nanosheets and optimizing the work function layer to lower threshold voltage effectively.
Implementation Method 1
a plasma enhanced atomic layer deposition (PEALD) process to form a nitrogen-rich titanium nitride work function layer at lower temperatures
Implementation Method 2
A method involving double-patterning or multi-patterning processes is used to form gate-all-around (GAA) transistors, including steps like ion implantation
Data Source
AI summary
A method of forming a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, the first semiconductor layers and the second semiconductor layers having different compositions, forming a dummy gate structure across the fin structure, forming gate spacers on opposite sidewalls of the dummy gate structure, respectively, removing the dummy gate structure to form a gate trench between the gate spacers, removing portions of the first semiconductor layers in the gate trench, such that the second semiconductor layers are suspended in the gate trench to serve as nanosheets, forming a first titanium nitride layer wrapping around the nanosheets, wherein an atomic ratio of titanium to nitrogen of the first titanium nitride layer is less than 1, and forming a metal fill layer over the first titanium nitride layer.