Backside Self-Aligned Power Rail Structure for GAA Short Isolation
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Solution Overview
Problem
Conventional power rail schemes in gate-all-around (GAA) devices face challenges such as low density, high resistance, and short circuit issues due to process limitations, leading to degraded semiconductor performance.
Innovation Solution
A self-aligned backside power rail scheme is implemented, utilizing a bottom dielectric layer to control via position and prevent short circuits between the metal gate and power rail, or between source and drain regions, by ensuring the via only connects to the source region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If existing power rail schemes are used in GAA devices, then power lines can be formed on the backside of the substrate, but the density is low and resistance is high due to process limitations
Solution Approach 1:
The patent forms power rails on the backside of the substrate in a different spatial dimension, utilizing the vertical thickness of the substrate to create self-aligned power rails that extend through the substrate. This dimensional approach allows for higher density power rails with better electrical characteristics by leveraging the third dimension (depth/thickness) rather than only planar arrangements.
Solution Approach 2:
The patent performs preliminary actions by forming the power rails and their associated vias simultaneously through a self-aligned process. The via holes are formed first, then the power rail material is deposited to fill these pre-formed holes, ensuring precise alignment and optimal electrical connection before subsequent device fabrication steps.
2Quantity of substance
If existing power rail schemes are used, then power lines can be formed on the backside, but isolation between the metal gate and the power line is very challenged
Solution Approach 1:
The patent introduces an intermediary dielectric layer that fills the space between the power rails and the metal gates. This dielectric material acts as an electrical insulator, preventing short circuits while allowing the power rails to be formed on the backside. The intermediary layer is carefully engineered to provide adequate isolation without interfering with the electrical performance of the power delivery network.
3Quantity of substance
If existing power rail schemes are used, then power lines can be formed on the backside, but short issue from the source region to the drain region may occur
Solution Approach 1:
The patent employs a self-aligned formation process where the via holes for power rail connection are automatically positioned to align with the source region, eliminating the need for separate alignment steps. This self-service approach ensures that power rails connect only to the intended source region without creating unintended short circuits to the drain region, as the alignment is inherent to the process geometry rather than relying on precise overlay control.
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.