Backside Gate Partial Cut Layout for Lower-Capacitance FinFETs
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Solution Overview
Problem
The challenge of scaling multi-gate transistors to smaller dimensions is hindered by lithographic constraints and trade-offs between feature size and spacing, leading to issues like increased device capacitance and potential device malfunction due to merged epitaxial structures and excessive gate electrode volume.
Innovation Solution
Implementing a backside partial cut process for metal gates and trench contacts, using sub-fin structures to reduce device capacitance by removing bulk gate metal and separating merged epitaxial structures, while utilizing self-aligned etching and planarization techniques to form efficient contact and gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistors are scaled to smaller dimensions, then device density is improved, but device capacitance increases and device malfunction occurs due to merged epitaxial structures
Solution Approach 1:
The patent introduces sub-fin structures that segment the continuous gate electrode into discrete portions. These sub-fin structures act as physical separators between adjacent epitaxial structures, preventing them from merging while maintaining high device density. The segmentation approach allows each transistor to retain its electrical integrity even at scaled dimensions.
Solution Approach 2:
The patent extracts or removes portions of the bulk gate metal using the sub-fin structures as etch stop layers. This extraction reduces the volume of gate metal that would otherwise contribute to excessive capacitance and potential merging issues, while still maintaining adequate gate control over the channel.
2Object-generated harmful factors
If gate electrode volume is reduced to decrease capacitance, then device capacitance is improved, but gate control over channel may be compromised
Solution Approach 1:
The patent applies local quality by creating regions of different gate metal thicknesses. The sub-fin structures ensure that gate metal is removed only in specific locations where epitaxial structures are present, while maintaining adequate gate metal volume in regions where channel control is critical. This localized approach reduces capacitance without compromising overall gate control.
Solution Approach 2:
The sub-fin structures serve as intermediary elements that mediate between the conflicting requirements of reduced capacitance and maintained gate control. These structures act as etch stop layers that selectively protect certain regions from gate metal removal, thereby controlling the final gate electrode geometry to balance capacitance reduction with channel control requirements.
3Reliability
If sub-fin structures are used to separate epitaxial structures, then device malfunction is reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent implements preliminary action by forming the sub-fin structures early in the fabrication process, before epitaxial growth and gate electrode formation. These pre-formed sub-fin structures serve as templates and etch stop layers that guide subsequent processing steps, ensuring proper separation of epitaxial structures without requiring complex later-stage interventions.
Solution Approach 2:
The sub-fin structures perform multiple functions automatically: they serve as physical separators between epitaxial structures, as etch stop layers during gate metal patterning, and as alignment references for subsequent processing steps. This multi-functionality reduces the need for additional separate process steps, thereby limiting the increase in manufacturing complexity.
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
Integrated circuit structures having a first fin in contact with and protruding above a trench isolation structure; a second fin laterally spaced apart from the first fin, the second fin in contact with and protruding above the trench isolation structure; and a gate electrode, wherein a first portion of the gate electrode is on top and along sidewalls of a protruding portion of the first fin, a second portion of the gate electrode is on top and along sidewalls of a protruding portion of the second fin, and a third portion of the gate electrode bridges the first and second portions of the gate electrode;