Backside Gate Contact Layout for Lower-Capacitance Semiconductor Routing

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Solution Overview

Problem

As semiconductor device size shrinks, the complexity of metal layer routing in intermetal connection layers increases, necessitating a solution to reduce capacitance and improve performance speed.

Innovation Solution

The formation of backside gate contacts and source/drain contacts on the substrate, along with self-aligned backside metal layer connections, reduces routing density and capacitance, enabling efficient local interconnection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If minimum feature size is reduced to increase integration density, then more components can be integrated into a given chip area, but metal layer routing complexity increases

Engineering Contradiction:
Improveintegration densityVSAvoidmetal layer routing complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent introduces backside gate contacts that extend through the substrate thickness dimension, allowing gate signals to be routed from the backside of the device. This adds a vertical routing dimension that reduces the burden on lateral metal layer routing, thereby decreasing routing complexity while maintaining high integration density

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Device complexity

If metal layer routing complexity increases, then more connections are needed, but capacitance increases and performance speed decreases

Engineering Contradiction:
Improverouting complexityVSAvoidcapacitance
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

The patent extracts the gate contact function from the traditional front-side metal routing layers and relocates it to the backside of the device. By taking out the gate signal path from the complex lateral routing network and providing a direct vertical path through the substrate, the number of metal layer connections is reduced, thereby decreasing total capacitance and improving performance speed

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20250364421A1Semiconductor devices with backside gate contacts and methods of fabrication thereof
Publication Date: 2025.11.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250364421A1 patent drawing
  • US20250364421A1 patent drawing
  • US20250364421A1 patent drawing

AI summary

Embodiments of the present disclosure provide a method for forming backside gate contacts and semiconductor fabricated thereof. A semiconductor device includes both signal outputs, such as source/drain contacts, and signal inputs, such as gate contacts, formed on a backside of the substrate. The backside gate contacts and backside source/drain contacts are formed in a self-aligned manner.