Self-Aligned Back-Side Gate Vias Using DSA Alignment Markers
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Solution Overview
Problem
The alignment of front- and back-side features in integrated circuit (IC) devices is insufficiently precise, particularly due to wafer distortions, which degrades device performance and prevents further down-scaling of transistor arrays.
Innovation Solution
The use of directed self-assembly (DSA) to form sacrificial materials aligned with front-side transistor structures, followed by self-aligned back-side contacts and vias, ensuring precise alignment through the formation of dielectric plugs with tell-tale seams.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional patterning methods are used to form back-side contacts and gate vias, then manufacturing process is simpler, but alignment precision between back-side patterns and front-side features deteriorates due to wafer distortions
Solution Approach 1:
The patent applies preliminary action by forming sacrificial structures on the front side of the wafer before back-side processing. These sacrificial structures serve as alignment references that are transferred to the back side through wafer bonding, enabling precise alignment of back-side contacts and gate vias with front-side transistor features despite wafer distortions during subsequent processing steps.
Solution Approach 2:
The patent uses sacrificial structures as intermediary elements that mediate the alignment between front-side and back-side features. These structures are formed on the front side, transferred to the back side through bonding, and then removed after serving their alignment function, thereby enabling precise feature registration without direct mechanical alignment during back-side patterning.
2Length of moving object
If wafer thickness is reduced to enable further down-scaling of transistor arrays, then device scaling is improved, but alignment precision between front- and back-side features deteriorates due to increased wafer distortion
Solution Approach 1:
The patent forms sacrificial structures on the front side before thinning the wafer and performing back-side processing. This preliminary action ensures that alignment references are established when the wafer is still thick and stable, allowing precise alignment to be maintained even as the wafer is thinned to enable further transistor down-scaling.
Solution Approach 2:
The sacrificial structures act as intermediary alignment markers that are transferred to the back side through bonding. These markers enable precise alignment of back-side features with front-side transistor features even in thinned wafers where traditional mechanical alignment would be insufficient due to increased distortion.
3Reliability
If traditional alignment methods are used, then manufacturing process is simpler, but device performance deteriorates due to misalignment errors
Solution Approach 1:
The patent performs preliminary formation of sacrificial structures on the front side with high precision before back-side processing. This preliminary action establishes accurate alignment references that ensure back-side contacts and gate vias are precisely aligned with front-side features, thereby maintaining high device performance despite the added process complexity.
Solution Approach 2:
The sacrificial structures serve as intermediary alignment markers that enable precise feature registration between front and back sides. These markers transfer alignment information through the wafer bonding process, ensuring that back-side features are correctly positioned relative to front-side transistor features, thus maintaining device performance.
Data Source
AI summary
Transistor structures between and coupled to front- and back-side interconnect layers may have precisely aligned arrays of contacts and dielectric structures over and under the transistor structures. Back-side dielectric plugs may electrically isolate source and drain regions contacted on the front side from back-side interconnect lines. Back-side dielectric plugs may have a seam indicating plug formation from the back side, and the seam may be on a side contacting a back-side interconnect line. Spacer layers may insulate back-side gate contacts from adjacent back-side contacts. Contacts and dielectric structures on a back side may be formed using directed self-assembly of sacrificial materials aligned to sacrificial structures on source and drain regions and revealed on a substrate back side.