Backside Guard Ring TSVs for Semiconductor Latch-Up Prevention
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Solution Overview
Problem
Existing semiconductor structures face challenges in preventing undesired conduction between PN junctions, which can lead to latch-up issues, requiring additional guard ring structures that occupy valuable chip space.
Innovation Solution
A semiconductor structure with a guard ring formed by doped regions and through-silicon vias (TSVs) on the backside of the wafer, eliminating the need for guard ring contacts on the topside by routing metal connections above the wafer, thereby reducing chip area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If guard ring structures are formed with contacts on the topside of the wafer, then undesired conduction between PN junctions is prevented, but chip area is occupied by the guard ring contacts and metal routing
Solution Approach 1:
The patent inverts the conventional guard ring contact location from the topside to the backside of the wafer. The guard ring contacts are now formed on the backside surface, and metal routing connects these backside contacts to the guard ring structures, eliminating the need for topside guard ring contacts and their associated metal routing, thus freeing up chip area while maintaining the prevention of undesired conduction between PN junctions
Solution Approach 2:
The patent moves the guard ring contacts from the two-dimensional topside surface to the backside surface of the wafer, effectively utilizing the third dimension (depth/thickness) of the wafer structure. This dimensional relocation allows the guard ring functionality to be implemented without occupying precious topside chip area, as the contacts and their metal routing are now located on the opposite surface of the wafer
2Reliability
If guard ring structures are formed to prevent latch-up issues, then device reliability is improved, but additional structures and routing are required
Solution Approach 1:
The patent merges the guard ring contact formation with the existing backside processing steps. The guard ring contacts are formed on the backside surface during the same fabrication sequence as other backside structures, and the metal routing is integrated with the existing metal layers. This merging approach implements the guard ring functionality without adding separate processing steps or structures, thereby improving reliability against latch-up without significantly increasing device complexity
Data Source
AI summary
A semiconductor structure includes a semiconductor wafer having a topside and a backside. The wafer includes a first semiconductor well of a first conductive type, a second semiconductor well of a second conductive type different from the first conductive type, a plurality of first semiconductor doped regions of the first conductive type and a plurality of first through silicon vias (TSVs) filled with conductive material. The first semiconductor well is formed within the second semiconductor well and exposed to the topside. The semiconductor device and the first semiconductor doped regions are formed within the first semiconductor well, and the first semiconductor doped regions surround the semiconductor device. Each first TSV extends into a corresponding one of the first semiconductor doped regions from the backside through the first and second semiconductor wells and is connected to a DC voltage or a ground potential from the backside.