Backside Interconnect Layout With Metal-Free Regions for Fault Detection
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Solution Overview
Problem
The complexity of manufacturing and fault detection in integrated circuit (IC) chips is increased due to the scaling down of semiconductor devices, as metal elements in back-side interconnect structures block optical signals emitted by semiconductor devices, hindering real-time fault detection.
Innovation Solution
Incorporation of metal-free keep-out regions in the back-side interconnect structure aligned with output terminals of standard cell circuits to allow unhindered propagation of optical signals for fault detection, using an automatic placement and routing tool to design these regions and prevent signal blockage by metal elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal elements are used in back-side interconnect structures to improve electrical connectivity, then electrical conductance is improved, but optical signal transmission is blocked hindering fault detection
Solution Approach 1:
The back-side interconnect structure is segmented into metal-containing regions for electrical connectivity and metal-free keep-out regions for optical signal transmission. This segmentation allows different functional requirements to be satisfied in different spatial zones of the same structure.
Solution Approach 2:
Different regions of the back-side interconnect structure have different material compositions: metal elements in regions requiring electrical conductance, and metal-free regions in areas requiring optical signal transmission. This local differentiation resolves the contradiction between electrical connectivity and optical detection.
2Productivity
If semiconductor devices are scaled down to increase storage capacity and processing speed, then device performance is improved, but manufacturing complexity and fault detection difficulty increase
Solution Approach 1:
The solution moves the interconnect structure to the back-side of the substrate, utilizing the third dimension (depth/thickness) to resolve the contradiction. By routing interconnects on the back-side rather than competing for space on the front-side, the patent enables continued device scaling while maintaining fault detection capability through keep-out regions.
3Ease of manufacture
If metal elements are placed in back-side interconnect structures to reduce manufacturing cost, then cost is reduced, but optical signal propagation is blocked
Solution Approach 1:
Metal elements are extracted from specific regions where they would block optical signals, creating metal-free keep-out regions. This selective removal of metal allows optical signal transmission while maintaining metal elements in regions where they provide electrical connectivity without interfering with detection.
Data Source
AI summary
The present disclosure describes a structure that includes a substrate with first and second sides, a device layer disposed on the first side of the substrate, having a fault detection area on a back-side surface of the device layer configured to emit a signal that is indicative of a presence or an absence of a defect in the device layer, a first interconnect structure disposed on a front-side of the device layer, and a second interconnect structure disposed on the second side of the substrate, having a metal-free region aligned with the fault detection area and a first metal layer having first and second conductive lines disposed substantially parallel to each other. First and second sidewalls of the first and second conductive lines, respectively, facing each other are substantially aligned with first and second sides of the fault detection area.