Backside Interconnect Layout for Flexible Routing and Lower IR Drop
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Solution Overview
Problem
The miniaturization of integrated circuits poses challenges in design and manufacturing, particularly in ensuring compliance with design rules and reducing IR drops while maintaining routing flexibility for backside conducting lines.
Innovation Solution
Incorporation of backside horizontal and vertical conducting lines with specific alignments and widths, along with pin-connectors, to mitigate design rule violations and reduce IR drops, allowing for flexible positioning without compromising layout area coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If backside conducting lines are used to improve routing flexibility, then design flexibility is improved, but IR drops increase
Solution Approach 1:
The patent applies local quality by varying the width of backside conducting lines based on their specific function and location. Power-related backside conducting lines are made wider to reduce IR drops, while signal lines maintain standard widths. This localized differentiation allows the system to achieve both routing flexibility and low energy loss by optimizing each conducting line's properties according to its specific requirements.
2Area of moving object
If miniaturization is pursued to reduce device size, then device size is reduced, but design rule compliance becomes more difficult
Solution Approach 1:
The patent resolves the miniaturization challenge by utilizing the backside of the substrate as an additional dimension for routing. Instead of confining all conducting lines to the front side, the invention extends the interconnect architecture to the backside, effectively adding a new spatial dimension for signal and power distribution. This approach allows continued device miniaturization on the front side while maintaining design rule compliance through the expanded backside routing space.
3Loss of energy
If backside conducting lines are positioned to reduce IR drops, then energy loss is reduced, but routing flexibility is compromised
Solution Approach 1:
The patent applies segmentation by dividing the backside conducting lines into functionally distinct segments: power delivery networks with wider traces optimized for low IR drops, and signal routing lines with standard widths maintaining design rule compliance. This segmentation allows different portions of the backside interconnect architecture to be optimized for their specific functions, simultaneously achieving low energy loss and routing flexibility through differentiated design strategies.
Data Source
AI summary
An integrated circuit includes a first-type active-region structure, a second-type active-region structure, and a plurality of gate-conductors at a front side of a substrate. The integrated circuit also includes a backside horizontal conducting line in a backside first conducting layer at a backside of the substrate, a backside vertical conducting line in a backside second conducting layer, and a pin-connector for a circuit cell. The backside first conducting layer is between the substrate and the backside second conducting layer. The pin-connector is directly connected between the backside horizontal conducting line and the backside vertical conducting line. The backside horizontal conducting line extends across a vertical boundary of the circuit cell by a distance that is less than one contacted poly pitch (“CPP”). One CPP is the pitch distance between two adjacent gate-conductors.