Semiconductor structure and manufacturing method thereof
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in creating smaller and more complex circuits while maintaining efficient production and reducing costs, particularly in the fabrication of advanced transistor structures.
Innovation Solution
The use of double-patterning or multi-patterning photolithography processes to create gate all-around (GAA) transistor structures and fin-like field-effect transistors (FinFETs), along with the integration of thermoelectric generator (TEG) devices to convert heat energy into voltage potential, enhancing manufacturing efficiency and power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scaling down geometry size to increase functional density, then production efficiency improves and costs lower, but manufacturing precision requirements worsen
Solution Approach 1:
The patent applies segmentation by dividing the patterning process into multiple stages through double-patterning or multi-patterning techniques. First, a preliminary pattern is formed, then additional patterns are added in subsequent steps to achieve the final complex circuit geometry. This allows each patterning step to work at relaxed dimensions while achieving ultra-fine final pitch, resolving the contradiction between scaling down geometry and maintaining manufacturing precision.
Solution Approach 2:
The patent transitions from two-dimensional planar transistors to three-dimensional FinFET structures with vertical fins extending from the substrate. This dimensional change allows increased functional density through the added vertical dimension while maintaining controllable pitch in the lateral dimension through multi-patterning, thus improving productivity without sacrificing manufacturing precision.
2Quantity of substance
If creating smaller and more complex circuits, then functional density increases, but device complexity worsens
Solution Approach 1:
The patent implements nesting by placing gate structures that completely surround transistor channels in three dimensions (gate-all-around configuration). The gate wraps around the channel from top, bottom, and sidewalls, creating a nested structure that provides maximum control over the channel while maintaining compact footprint. This allows higher functional density without proportionally increasing device complexity.
Solution Approach 2:
By transitioning to FinFET and GAA structures, the patent adds vertical dimensionality to control current flow. The vertical fins and surrounding gates provide enhanced electrostatic control and packing density without requiring proportional increases in lateral circuit complexity, as the vertical structures self-organize through the manufacturing process.
3Length of moving object
If using double-patterning or multi-patterning processes, then pitch decreases, but manufacturing complexity worsens
Solution Approach 1:
The patent applies preliminary action by first forming a sacrificial pattern or mandrel structure, then using it as a template for subsequent pattern formation. The preliminary pattern guides the deposition of spacer materials or additional pattern layers, ensuring precise pitch control. This preliminary structuring simplifies the overall multi-patterning process by providing a reference framework for subsequent steps.
Solution Approach 2:
The patent uses intermediary materials such as spacer layers deposited conformally on preliminary patterns. These intermediary spacers act as mediators that transfer the preliminary pattern geometry into the final circuit pattern with reduced pitch. The intermediary layer facilitates the transformation from one pattern scale to another without requiring direct high-precision patterning at the final dimension.
4Loss of energy
If integrating thermoelectric generators, then power management efficiency improves, but device complexity worsens
Solution Approach 1:
The patent merges the thermoelectric generator function with the existing transistor structure by integrating TEG materials into the substrate or device interlayers. The TEG converts waste heat from transistor operation into useful voltage to power embedded memory or pre-charge capacitors. This merging approach adds energy recovery functionality without requiring completely separate power management structures, thus improving energy efficiency while limiting increases in overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the production of smaller, more complex circuits with improved manufacturing efficiency and power management capabilities, enabling immediate refresh of embedded memories and power storage in semiconductor structures.
Implementation Method 1
integration of thermoelectric generators (TEGs) to convert heat energy into voltage
Data Source
AI summary
A semiconductor structure includes a substrate, a device, a conductor, a backside interconnect, and a thermoelectric generator. The substrate has a front surface and a rear surface opposite to the front surface. The device is disposed on the front surface of the substrate. The conductor is disposed at or near the front surface of the substrate and electrically coupled to the device. The backside interconnect is disposed on the rear surface of the substrate and electrically coupled to the device. The thermoelectric generator is disposed in the substrate and electrically coupled to the device, and includes a first-type through via and a second-type through via. The first-type through via penetrates from the rear surface of the substrate to the conductor, and is connected to a first conductive feature of the backside interconnect and the conductor. The second-type through via penetrates from the rear surface of the substrate to the conductor, and is connected to a second conductive feature of the backside interconnect and the conductor. The second-type through via is different from the first-type through via.