Backside Isolation Biasing in Stacked CMOS Image Sensors
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Solution Overview
Problem
As CMOS image sensors shrink in size, cross-talk between pixels increases, reducing quantum efficiency and image sensor performance, existing isolation structures are insufficient in addressing these issues.
Innovation Solution
A negative bias circuit is coupled to a peripheral region of the image sensor, applying a negative bias to the backside isolation structure, which reduces electron holes and electrical conductance, thereby decreasing cross-talk and enhancing quantum efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If pixel size is reduced to increase sensor density, then sensor size and cost are reduced, but cross-talk between pixels increases and quantum efficiency decreases
Solution Approach 1:
The patent divides the semiconductor substrate into distinct pixel regions separated by isolation structures. Each pixel is isolated from its neighbors through etched trenches filled with dielectric material, creating discrete sensing elements that prevent electrical cross-talk while maintaining small physical dimensions for high density.
Solution Approach 2:
The patent applies different material properties and structural characteristics to different regions of the substrate. Isolation structures use dielectric materials with specific electrical properties to block charge carrier migration between pixels, while photodetector regions maintain high conductivity for signal generation. This localized differentiation enables small pixel sizes without compromising quantum efficiency.
2Reliability
If isolation structures are added to reduce cross-talk, then pixel performance is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent combines multiple functions into the isolation structure: it serves as both a physical separator between pixels and an electrical barrier through its dielectric properties. The same structure that defines pixel boundaries also prevents charge carrier migration, eliminating the need for separate isolation and blocking mechanisms.
Solution Approach 2:
The isolation structures perform multiple roles simultaneously: they provide mechanical support, define pixel geometry, prevent electrical cross-talk, and manage stress in the substrate. This multi-functionality reduces the need for additional specialized components, simplifying overall device architecture despite the added isolation requirements.
3Ease of manufacture
If conventional isolation structures are used, then manufacturing is simpler, but cross-talk reduction is insufficient for small pixel sizes
Solution Approach 1:
The patent modifies key parameters of the isolation structures, including increasing dielectric layer thickness, adjusting trench depth and width ratios, and selecting materials with higher breakdown voltages. These parameter changes enhance the electrical isolation capability to prevent cross-talk in small pixels while maintaining compatibility with standard semiconductor fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of a negative bias circuit improves the sensing performance and accuracy of images produced by reducing cross-talk between photodetectors and increasing quantum efficiency.
Implementation Method 1
A negative bias circuit is coupled to a peripheral region of the image sensor, applying a negative bias to the backside isolation structure, which reduces electron holes and electrical conductance
Data Source
AI summary
Some embodiments relate to an image sensor. The image sensor includes a semiconductor substrate including a pixel region and a peripheral region. A backside isolation structure extends into a backside of the semiconductor substrate and laterally surrounds the pixel region. The backside isolation structure includes a metal core, and a dielectric liner separates the metal core from the semiconductor substrate. A conductive feature is disposed over a front side of the semiconductor substrate. A through substrate via extends from the backside of the semiconductor substrate through the peripheral region to contact the conductive feature. The through substrate via is laterally offset from the backside isolation structure. A conductive bridge is disposed beneath the backside of the semiconductor substrate and electrically couples the metal core of the backside isolation structure to the through substrate via.