Backside Memory Bit Line Routing to Reduce Resistance and Coupling
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Solution Overview
Problem
The semiconductor industry faces challenges with electrical resistance and coupling effects in memory devices as technology advances towards smaller scales and increased complexity.
Innovation Solution
A semiconductor structure with front-side and backside redistribution structures, utilizing different materials for metal lines to reduce electrical resistance and coupling effects, and optimizing signal routing through dual redistribution layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If signal transmission lines are placed on the front side of the substrate, then routing resources are sufficient, but electrical resistance increases and coupling effects occur
Solution Approach 1:
The patent moves signal transmission from the traditional front-side plane to the backside of the substrate, utilizing the third dimension (substrate thickness) to create separate signal paths. This dimensional transition allows bit lines and word lines to be routed on opposite sides of the substrate, reducing electrical resistance and minimizing coupling effects between intersecting signal lines.
2Reliability
If backside redistribution structure is used, then electrical resistance is reduced and coupling effects are minimized, but manufacturing complexity increases
Solution Approach 1:
The patent divides the substrate into distinct functional regions: the front side contains the transistor array and memory cells, while the back side contains the redistribution structure with signal transmission lines. This segmentation allows each side to be optimized independently, with the backside redistribution layer handling high-speed signal transmission away from the active device region, thereby reducing interference and simplifying the overall manufacturing process.
3Productivity
If smaller product scales are pursued, then device density increases, but electrical resistance and coupling effects worsen
Solution Approach 1:
By transitioning signal routing to the backside of the substrate and utilizing vertical stacking, the patent enables higher device density on the front side without compromising signal transmission quality. The separated routing paths on the backside maintain adequate signal integrity even as device dimensions are reduced, allowing continued scaling while preserving reliability.
Data Source
AI summary
A semiconductor structure includes a substrate, a data storage element, and first and second bit line sets. The substrate has a front side and a backside and includes a substrate layer, a first active layer, and a second active layer. The second active layer is proximal to the front side. The substrate layer is proximal to the backside. The data storage element extends across the first and second active layers. The first bit line set includes a first bit line and a first complementary bit line. At least one of the first bit line and the first complementary bit line is disposed on the front side of the substrate. The second bit line set includes a second bit line and a second complementary bit line. At least one of the second bit line and the second complementary bit line is disposed on the backside of the substrate.