Backside-Isolated OTP Memory Structure for Leakage Control
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Solution Overview
Problem
Existing gate-all-around (GAA) devices face challenges with current leakage, especially under high current, high voltage, or high speed conditions, and existing methods for fabricating these devices do not adequately address the issue of current leakage while maintaining circuit packing density and power efficiency.
Innovation Solution
The proposed solution involves thinning down the semiconductor substrate from the backside to expose shallow trench isolation structures, forming backside vias and dielectric layers to isolate semiconductor islands, and implementing a backside interconnect structure to reduce current leakage and enhance isolation, thereby eliminating well pickup regions and reducing device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If GAA devices are scaled down to improve gate control and reduce SCEs, then gate-channel coupling is improved, but current leakage increases under high current, high voltage, or high speed conditions
Solution Approach 1:
The device is segmented into multiple semiconductor islands separated by isolation structures. Each island contains individual GAA devices, physically dividing the device structure to contain and control current flow paths, thereby reducing current leakage while maintaining gate control in scaled devices
Solution Approach 2:
Isolation structures serve as intermediary elements between adjacent semiconductor islands. These structures act as mediators that block current leakage paths while allowing the GAA devices on each island to maintain their gate control, effectively separating the harmful current leakage from the functional device regions
2Object-generated harmful factors
If isolation structures are added to reduce current leakage, then current leakage is reduced, but device area increases
Solution Approach 1:
The isolation approach transitions from planar isolation to three-dimensional isolation by forming isolation structures that extend through the substrate and laterally between islands. This dimensional approach allows more effective current leakage blocking with reduced lateral footprint, maintaining high circuit packing density while reducing current leakage
Data Source
AI summary
The present disclosure provides an integrated circuit (IC) structure that includes a semiconductor substrate having a frontside and a backside; a shallow trench isolation (STI) structure formed in the semiconductor substrate and defining an active region, wherein the STI structure includes a STI bottom surface, wherein the semiconductor substrate includes a substrate bottom surface, and wherein the STI bottom surface and the substrate bottom surface are coplanar; a field-effect transistor (FET) over the active region and formed on the frontside of the semiconductor substrate; and a backside dielectric layer disposed on the substrate bottom surface and the STI bottom surface.