Backside PN Junction Diode Routing
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Solution Overview
Problem
The aggressive scaling of integrated circuit (IC) dimensions has led to densely spaced gate structures and source/drain contacts, posing challenges for back-side routing and contact resistance in semiconductor manufacturing.
Innovation Solution
The implementation of multi-bridge-channel (MBC) transistors with epitaxial layers and silicide layers to reduce contact resistance and enable effective back-side routing, while also incorporating PN junction diode structures for enhanced circuit functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If aggressive scaling of IC dimensions is implemented, then production efficiency is improved and costs are lowered, but gate structures and source/drain contacts become densely spaced making routing difficult
Solution Approach 1:
The patent moves routing features from the front side to the back side of the substrate, utilizing the third dimension (depth/thickness) to resolve the routing congestion caused by aggressive scaling. This allows routing to occur in a different spatial plane, avoiding interference with densely packed gate structures and source/drain contacts on the front side.
2Adaptability or versatility
If conventional back-side routing techniques are used, then routing capabilities are improved, but contact resistance remains high
Solution Approach 1:
The patent introduces an intermediary structure (the back-side contact structure with specific material composition and geometry) that mediates between the routing requirement and the contact resistance issue. This intermediary structure provides a low-resistance path while enabling back-side routing, resolving the conflict between routing capability and contact resistance.
3Reliability
If multi-gate devices are introduced to improve gate control, then gate-channel coupling is increased, but gate structures become densely spaced
Solution Approach 1:
The patent utilizes the back side of the substrate as an additional dimension for routing, allowing multi-gate devices to be densely packed on the front side without compromising routing capabilities. This dimensional separation enables aggressive scaling of gate structures while maintaining adequate routing space.
Data Source
AI summary
The present disclosure provides embodiments of semiconductor devices. A semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer.