Nanoinformatics TRIZ Cases
- Horizontal Nanowire Formation via Selective Oxidation
Selective oxidation of SiGe sacrificial layers enables uniform critical dimension control for scalable gate-all-around field effect transistors.
- Wafer-Scale Plasmonic Substrates with Tunable Nanogaps
Deep UV lithography and focused ion beam milling create reproducible sub-5 nm gaps, resolving wafer-scale fabrication precision limits.
- Carbon Nanotube Phase Change Memory Contact Area Reduction
Carbon nanotube bottom electrodes reduce operation current by increasing resistance and local heat generation, overcoming uniformity limitations.
- GaN Transistor Linearity via Segmented Channel Design
A segmented channel structure in GaN transistors constrains current-carrying capability under the gate to enhance device linearity.
- Semiconductor Source/Drain Patterns with Graded Germanium Concentration
A semiconductor device uses source/drain patterns with graded germanium concentrations to enhance electric characteristics.
- Switching Atomic Transistor with Diffusion Barrier Layer
A switching atomic transistor introduces a diffusion barrier layer to stabilize ion concentration, resolving resistance change layer instability.
- Back-Gated FDSOI Transistor with Body Contact for Charge Extraction
A back-gated FDSOI transistor uses a conductive body contact to extract minority carriers, preventing snap-back caused by hole accumulation during programming.
- SiGe Source Drain Ge Gradient Nanowire Strain
High temperature oxidation drives silicon removal and germanium diffusion to increase core concentration and impart compressive strain.
- Semiconductor Memory Device Using Paired Bit Lines
A semiconductor memory device uses paired bit lines formed by the same interconnection layer to reduce manufacturing complexity.
- Fibre Optic Quantum Memory with Nonlinear Switching
A fibre optic quantum memory system uses a nonlinear optical switching mechanism to trap and release stored quantum states of light within an integrated optical cavity.
- Dual-Strained Nanowire FinFETs with Dielectric Isolation
Dielectric isolation layers on a SiGe buffer prevent Ge diffusion leakage while maintaining tensile and compressive channel strain.
- Nano Dot Stabilizes Reset Current in Nonvolatile Memory Oxide Layer
A nano dot within the oxide layer unifies current paths to stabilize reset current values.
- Nanostructured Device Direct Contact Nanowire Growth
A nanostructured device uses a patterned buffer layer to enable direct electrical contact with nanowire junctions.
- Solar Cell System with Carbon Nanotube Interconnects
Carbon nanotube interconnects reduce internal resistance and eliminate front electrode obstruction to boost photoelectric conversion efficiency.
- Nanosheet Transistor Integration with Thick Gate Dielectrics
A nanosheet transistor fabrication method uses selective sacrificial layer removal to enable coplanar integration of thin and thick gate dielectric devices.
- Nitride Semiconductor Device With Asymmetric Quantum Wells
An asymmetric quantum well structure with a tunneling barrier improves light emission intensity at high current densities.
- I-Shaped Fin VFET Parasitic Resistance Reduction
Self-aligned silicon oxide nanomasks prevent tapered oxidation, maintaining wider conduction paths at the top junction to lower parasitic resistance.
- Direct Magnetic Tunnel Junction Communication via Nano-Magnetic Channel
Nano-magnetic channels connect magnetic tunnel junctions directly, eliminating intermediate circuitry to reduce integration complexity and power consumption.
- Vertical Silicon Nanowire Transistor Fabrication for Low Parasitic Resistance
A vertical silicon nanowire field effect transistor fabrication method reduces parasitic resistance through selective area growth and sacrificial layer removal.
- Carbon Nanotube Neuron Device Structure
A carbon nanotube neuron device structure integrates multi-layer film electrodes to control channel conductivity.
- CMOS Gate-All-Around Transistor Channel Orientation
Independent channel orientation layout aligns nanosheet surfaces with specific crystal planes to resolve carrier mobility degradation caused by interface traps.
- Backside PN Junction Diode Routing
Backside routing via a PN junction diode with silicide layers resolves high contact resistance and gate spacing constraints.