SiGe Source Drain Ge Gradient Nanowire Strain
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Solution Overview
Problem
The challenge in integrated circuit fabrication lies in achieving high-quality embedded epitaxial source or drain (Epi S/D) structures with high germanium content to maintain strain in nanoribbon channels, which is crucial for improving device performance, as conventional methods often result in defective Epi S/D with low germanium concentration and tensile stress, degrading drive current.
Innovation Solution
A condensation technique is implemented to repair defects and increase the effective germanium concentration in Epi S/D structures, involving a high-temperature anneal in an oxidizing environment that causes silicon to oxidize preferentially, allowing germanium to diffuse inward and concentrate in the core, thereby enhancing compressive strain and channel performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional epitaxial growth methods are used to form source or drain structures, then the fabrication process is simpler and cost is lower, but the germanium concentration remains low and defects are present, degrading device performance
Solution Approach 1:
A silicon oxide layer is formed on the surface of the epitaxial source or drain structure before the condensation process. This preliminary action protects the surface during high-temperature annealing and enables controlled germanium diffusion inward from the surface, achieving high germanium concentration in the core region without requiring complex in-situ doping processes.
Solution Approach 2:
The patent utilizes the harmful effect of silicon oxidation at high temperatures to achieve beneficial germanium enrichment. By intentionally oxidizing the surface in an oxygen ambient, silicon is removed preferentially while germanium diffuses inward and concentrates, transforming a potential defect (oxidation) into a useful mechanism for achieving high germanium concentration.
2Reliability
If high germanium content is introduced to maintain strain in nanoribbon channels, then device performance and drive current are improved, but conventional methods result in low germanium concentration and tensile stress, contradicting the desired compressive strain
Solution Approach 1:
The patent changes the physical and chemical parameters of the epitaxial structure through high-temperature annealing (e.g., 900-1100°C) in an oxygen ambient. This parameter change triggers preferential silicon oxidation and germanium diffusion, transforming the germanium concentration profile from uniform and low to graded and high in the core, thereby achieving the desired compressive strain and improved device performance.
Solution Approach 2:
Instead of relying on mechanical strain engineering during epitaxial growth, the patent substitutes a chemical mechanism (oxidation-driven diffusion) to achieve strain. The chemical process of silicon oxidation and germanium redistribution naturally creates compressive strain in the channel region, replacing the need for complex mechanical strain control methods.
3Productivity
If the critical dimension of features is reduced to increase device density, then more functional units fit on the chip, but the spacing between features becomes constrained, making lithographic patterning increasingly difficult
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional gate-all-around nanowire structures. This dimensional change increases the effective channel width and device density without proportionally reducing the lithographic critical dimension, as the gate wraps around the nanowire channel in three dimensions, providing superior control and performance at scaled dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in Epi S/D structures with an effective germanium concentration greater than 30%, effectively imparting compressive strain to the channel, improving device performance by enhancing drive current and reducing defects.
Implementation Method 1
a high-temperature anneal in an oxidizing environment that causes silicon to oxidize preferentially
Implementation Method 2
allowing germanium to diffuse inward and concentrate in the core
Implementation Method 3
a high-temperature anneal in an oxidizing environment
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
Integrated circuit structures having condensed source or drain structures (152) with high germanium content are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires (108). A gate stack (110) is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure (152) is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure (152) is at a second end of the vertical arrangement of horizontal nanowires. Each of the first and second epitaxial source or drain structures includes silicon and germanium, the atomic concentration of germanium having a gradient between a core and the periphery of the epitaxial source or drain structure. The gradient is achieved using a high temperature anneal of SiGe source or drain structures in an oxidizing environment and the resulting Ge condensation.