Semiconductor Source/Drain Patterns with Graded Germanium Concentration

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Solution Overview

Problem

The scaling down of MOS-FETs in semiconductor devices leads to deterioration in operational properties, necessitating improvements in electric characteristics.

Innovation Solution

A semiconductor device with a substrate having a center and edge region, featuring active patterns, channel patterns, source/drain patterns, and gate electrodes. The source/drain patterns include a buffer layer and a main layer with varying germanium concentrations, optimized for improved electric characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If MOS-FETs are scaled down to meet increasing demand for small pattern size, then device density is improved, but operational properties deteriorate

Engineering Contradiction:
Improvepattern sizeVSAvoidoperational properties
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The patent applies local quality by implementing different germanium concentrations in different regions of the source/drain patterns. The first semiconductor layer has a first germanium concentration while the second semiconductor layer has a second germanium concentration, creating localized compositional gradients that optimize device performance in specific areas without compromising overall scaling benefits

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the material composition parameter by incorporating germanium at varying concentrations in the source/drain patterns. This parameter modification allows optimization of carrier concentration and mobility in the semiconductor channels, thereby improving operational properties while maintaining scaled-down dimensions

Inventive Principle:
Principle #35Parameter changes

2Reliability

If germanium concentration is increased in the first semiconductor layer on the center region, then electric characteristics are improved, but manufacturing uniformity becomes more difficult to control

Engineering Contradiction:
Improveelectric characteristicsVSAvoidgermanium concentration uniformity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The source/drain pattern is segmented into multiple semiconductor layers with distinct germanium concentrations. The first semiconductor layer and second semiconductor layer are formed sequentially with controlled composition gradients, allowing independent optimization of each layer's properties while maintaining overall manufacturing control through staged fabrication processes

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a vertical dimension to the germanium concentration variation by forming multiple semiconductor layers stacked vertically. Instead of uniformly increasing germanium concentration in a single layer (which would create manufacturing uniformity issues), the composition is varied across different vertical layers, allowing spatial distribution of germanium that improves electric characteristics while maintaining manufacturing precision

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The semiconductor device achieves improved electric characteristics by optimizing germanium concentrations in the source/drain patterns, enhancing performance and uniformity across the device.

Implementation Method 1

Each of the first source/drain pattern and the second source/drain pattern may include a buffer layer and a main layer on the buffer layer... The main layer may include a first semiconductor layer and a second semiconductor layer on the first semiconductor layer

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS12328921B2Semiconductor device and method of fabricating the same
Publication Date: 2025.06.10 SAMSUNG ELECTRONICS CO LTD
  • US12328921B2 patent drawing
  • US12328921B2 patent drawing
  • US12328921B2 patent drawing

AI summary

A semiconductor device may include a substrate including center and edge regions, active patterns on the substrate, channel patterns on the active patterns, source/drain patterns connected to the channel patterns, and gate electrodes on the channel patterns. Each of the source/drain patterns may include a buffer layer in contact with a corresponding one of the channel patterns and a main layer on the buffer layer. The main layer of each of the source/drain patterns may include first and second semiconductor layers, which may be sequentially stacked and contain germanium. A concentration of the germanium in the first semiconductor layer may be higher on the center region than on the edge region, and a concentration of the germanium in the second semiconductor layer may be lower on the center region than on the edge region.