Semiconductor Memory Device Using Paired Bit Lines
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Solution Overview
Problem
Conventional MRAM devices require a large write current due to the indirect current-induced magnetic field write method, which increases with smaller MTJ element sizes, and have a high process cost and long chip formation period due to the use of different interconnection layers for paired bit lines.
Innovation Solution
The semiconductor memory device uses paired bit lines formed by the same interconnection layer, with transistors and word lines arranged to reduce the number of interconnection layers, allowing for a more efficient and cost-effective chip formation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If different interconnection layers are used for paired bit lines, then the bit lines can be independently routed, but the number of interconnection layers increases, leading to high process cost and long chip formation period
Solution Approach 1:
The patent merges the routing function of paired bit lines into a single interconnection layer. Specifically, first and second bit lines are formed in the same interconnection layer, allowing them to be routed independently while sharing the same manufacturing layer, thereby reducing the total number of interconnection layers required in the device structure
Solution Approach 2:
The single interconnection layer serves multiple functions by carrying both first and second bit lines, which would traditionally require separate dedicated layers. This multi-functional use of the interconnection layer reduces manufacturing complexity and process cost while maintaining the necessary electrical routing functionality
2Reliability
If current-induced magnetic field write method is used, then magnetization reversal can be achieved, but the write current becomes large, especially when MTJ element is downsized
Solution Approach 1:
The patent introduces a spin injection mechanism as an intermediary write method. Instead of directly using current-induced magnetic fields, the invention uses spin-polarized current injection through the MTJ element to induce magnetization reversal via spin transfer torque, which is more efficient especially for downsized elements
Solution Approach 2:
The patent changes the write mechanism from magnetic field induction to spin transfer torque by altering the physical parameters of the write process. This involves changing from a field-based approach to a direct spin-momentum transfer approach, which reduces the required write current density particularly in scaled-down MTJ structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the process cost and shortens the chip formation period while maintaining efficient data storage capabilities, as the same interconnection layer for bit lines minimizes the number of layers required, achieving a smaller cell size without increasing memory cell area.
Implementation Method 1
This semiconductor memory stores information by using a so-called magnetoresistive effect by which the resistance value changes in accordance with relative magnetization directions in the recording layer and fixed layer
Implementation Method 2
This write method reverses the magnetization direction in the recording layer by a magnetic field induced by an electric current flowing through a write line
Implementation Method 3
a so-called spin injection MRAM using magnetization reversal caused by polarized spin current injection
Data Source
AI summary
A semiconductor memory device includes the first transistor having first and second source/drain diffusion regions positioned below a second bit line to sandwich the first word line therebetween, and the second source/drain diffusion region positioned between the first and second word lines and connected to a first bit line, a second transistor having second and third source/drain diffusion regions positioned below the second bit line to sandwich the second word line therebetween, a first resistive memory element formed below the second bit line above the first source/drain diffusion region, and having terminals connected to the second bit line and the first source/drain diffusion region, and a second resistive memory element formed below the second bit line above the third source/drain diffusion region, and having terminals connected to the second bit line and the third source/drain diffusion region.