GaN Transistor Linearity via Segmented Channel Design
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Solution Overview
Problem
GaN-based transistors exhibit non-linear behavior at high drain currents due to increasing access resistance, limiting their linearity and maximum operating frequency, especially as gate length scales down, which is a challenge for large-signal RF operation.
Innovation Solution
The solution involves reducing the current-carrying capability under the gate by limiting the semiconductor material in the channel region, either by reducing its width or forming multiple channels with regions of limited conductivity, to prevent current limitation by the source or drain access regions, thereby enhancing linearity and operating range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the gate length is reduced to increase operating frequency, then the maximum operating frequency is improved, but the linearity deteriorates due to increasing access resistance
Solution Approach 1:
The channel region is segmented into multiple sub-channels separated by regions of limited conductivity. This segmentation allows each sub-channel to carry a portion of the total current, reducing the current density and access resistance in each individual channel, thereby maintaining linearity at higher operating frequencies.
Solution Approach 2:
Different regions of the semiconductor structure are given different conductivity properties. The channel regions have high conductivity for current flow, while the separating regions have limited conductivity to divide the current paths. This local differentiation of electrical properties enables the device to maintain linearity while operating at reduced gate lengths for higher frequency performance.
2Reliability
If the current-carrying capability under the gate is reduced to improve linearity, then the linearity is improved, but the current handling capacity deteriorates
Solution Approach 1:
Instead of reducing the total channel width, the channel is divided into multiple parallel sub-channels. Each sub-channel has reduced current-carrying capability individually, but collectively they maintain the total current handling capacity while improving linearity through reduced access resistance in each segment.
Solution Approach 2:
Multiple sub-channels are combined in parallel to achieve the desired total current handling capacity. Each sub-channel contributes a portion of the total current, and their combined effect maintains power handling while the segmented structure improves linearity by reducing the access resistance burden on any single current path.
3Reliability
If multiple channels with regions of limited conductivity are formed to prevent current limitation, then the linearity is improved, but the device complexity increases
Solution Approach 1:
The complexity is localized to specific regions between the channels rather than throughout the entire device. The regions of limited conductivity are confined to narrow separating zones, while the channel regions themselves maintain simple, uniform structures. This localized approach to creating multiple current paths minimizes the overall device complexity while achieving improved linearity.
Data Source
AI summary
A field effect transistor that has a source, a drain, a gate and a semiconductor region. The semiconductor region has a source access region between the gate and the source, a drain access region between the gate and the drain, and a channel region under the gate. The channel region under the gate has a maximum current-carrying capability that is lower than a maximum current-carrying capability of the source access region.