Back-Gated FDSOI Transistor with Body Contact for Charge Extraction
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Solution Overview
Problem
Traditional Fully Depleted Semiconductor-on-Insulator (FDSOI) transistors experience charge accumulation due to hole generation from impact ionization during hot carrier injection programming, leading to snap-back issues in non-volatile memory applications.
Innovation Solution
A back-gated non-volatile memory device is developed with a storage layer and a conductive region formed on the channel, allowing for minority carrier escape paths, achieved through wafer bonding, cleaving, and epitaxial growth of source/drains with a sidewall spacer, preventing charge accumulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hot carrier injection programming is used in FDSOI transistors, then non-volatile memory programming is achieved, but hole accumulation in the body occurs causing snap-back
Solution Approach 1:
The patent extracts the harmful holes generated during hot carrier injection by providing an escape path through a conductive region (such as a heavily doped source/drain region or separate contact) connected to the body. This removes the accumulated charge that would otherwise cause snap-back, while preserving the programming capability.
Solution Approach 2:
The patent introduces an intermediary conductive region or body contact structure that mediates between the floating body and the external circuit. This intermediary provides a controlled path for hole extraction, preventing direct accumulation in the channel while enabling safe discharge of generated carriers.
2Reliability
If floating body structure is used in FDSOI transistors, then reduced short channel effects are achieved, but charge accumulation occurs during programming
Solution Approach 1:
The patent transforms the static floating body structure into a dynamic system where the body potential can be actively controlled. By adding body contacts or conductive regions, the body is no longer completely floating but can be dynamically adjusted to prevent charge accumulation while maintaining the beneficial short channel effects.
Solution Approach 2:
The patent changes the electrical parameters of the body region by introducing conductive paths that alter the body's charge state. This allows the body to transition from a completely floating state to a partially controlled state, preventing harmful charge accumulation while preserving device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents charge accumulation in the channel, enhancing the reliability and performance of FDSOI transistors by providing an escape path for minority carriers generated during programming.
Implementation Method 1
A storage layer is formed on the gate
Implementation Method 2
epitaxially growing the source/drains laterally from the channel
Implementation Method 3
bonding two wafers
Data Source
AI summary
A method of making a semiconductor device includes providing a first wafer and providing a second wafer having a first side and a second side, the second wafer including a semiconductor substrate, a storage layer, and a layer of gate material. The storage layer may be located between the semiconductor structure and the layer of the gate material and the storage layer may be located closer to the first side of the second wafer than the semiconductor structure. The method further includes boding the first side of the second wafer to the first wafer. The method further includes removing a first portion of the semiconductor structure to leave a layer of the semiconductor structure after the bonding. The method further includes forming a transistor having a channel region, wherein at least a portion of the channel region is formed from the layer of the semiconductor structure.