Backside-Power Chip Package Architecture for Dense Interconnect Routing
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Solution Overview
Problem
Current interconnect technologies in IC packaging suffer from low vertical and horizontal interconnect density, leading to routing congestion and power delivery limitations, especially in monolithic ICs with diverse circuit requirements.
Innovation Solution
A quasi-monolithic packaging architecture using double-sided metallization stacks with high-density interconnects between IC dies, featuring conductive traces on one side and thin traces on the backside for improved power distribution and signal routing, coupled with through-dielectric vias and a support structure for enhanced connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional single-sided metallization is used in IC packaging, then manufacturing process is simple, but interconnect density is low and routing congestion occurs
Solution Approach 1:
The patent transitions from single-sided metallization to double-sided metallization stacks, adding a vertical dimension to interconnect routing. This allows interconnects to be formed on both the front and back sides of the substrate, effectively doubling the available interconnect pathways and significantly increasing interconnect density without complicating the fundamental manufacturing process.
Solution Approach 2:
The patent implements nested metallization stacks where multiple conductive layers are stacked vertically on both sides of the substrate. Each layer is embedded within dielectric material, creating a nested structure that maximizes interconnect density within the available volume while maintaining manufacturing feasibility through standard semiconductor fabrication processes.
2Productivity
If monolithic IC architecture is used, then manufacturing is efficient, but power delivery limitations occur in circuits with diverse requirements
Solution Approach 1:
The patent applies local quality by creating separate power delivery pathways on the back side of the substrate, allowing different regions of the IC to receive power optimized for their specific requirements. This enables high-power circuits to have dedicated power delivery routes independent of signal routing, improving overall power delivery capability while maintaining monolithic manufacturing efficiency.
Solution Approach 2:
The patent segments power delivery and signal routing functions into separate metallization layers and locations. Power delivery is handled through dedicated traces and vias on the back side, while signal routing occurs on the front side and intermediate layers. This segmentation allows each function to be optimized independently, improving power delivery to circuits with diverse requirements.
3Quantity of substance
If interconnect density is increased to reduce routing congestion, then signal routing improves, but manufacturing complexity increases
Solution Approach 1:
The patent uses another dimension (the back side of the substrate) to accommodate increased interconnect density. By forming metallization stacks on both sides of the substrate, the patent achieves high interconnect density without increasing lateral complexity, as the additional interconnects are distributed in the vertical and bilateral dimensions rather than crowding a single plane.
Data Source
AI summary
Embodiments of a microelectronic assembly comprise: a plurality of layers of integrated circuit (IC) dies, each layer coupled to adjacent layers by first interconnects having a pitch of less than 10 micrometers between adjacent first interconnects; an end layer in the plurality of layers proximate to a first side of the plurality of layers comprises a dielectric material around IC dies in the end layer and a through-dielectric via (TDV) in the dielectric material of the end layer; a support structure coupled to the first side of the plurality of layers, the support structure comprising a structurally stiff base with conductive traces proximate to the end layer, the conductive traces coupled to the end layer by second interconnects; and a package substrate coupled to a second side of the plurality of layers, the second side being opposite to the first side.