Backside Power Mesh Layout for Low-Resistance Semiconductor Routing
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Solution Overview
Problem
As semiconductor devices miniaturize, the complexity of manufacturing increases, leading to issues such as high yield loss, reduced reliability of electrical interconnections, and low testing coverage, necessitating improvements in device robustness and manufacturing efficiency.
Innovation Solution
A backside power rail scheme is introduced, where the front-side area is used for signal lines and the backside area for power rails, enlarging the routing area for power rails to reduce resistance and capacitance, thereby maintaining or improving device performance despite reduced device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If power rails are routed only on the front side of the substrate, then the routing area is limited, but the device performance deteriorates due to increased resistance and capacitance
Solution Approach 1:
The patent applies dimensionality change by routing power rails on both the front side and back side of the substrate, utilizing the third dimension (depth/thickness) to create additional routing space. This allows the power distribution network to expand from a single-plane configuration to a multi-layer spatial arrangement, effectively increasing the total routing area while reducing resistance and capacitance through shorter and more direct power delivery paths.
2Productivity
If device size is reduced to increase functional density, then more devices fit per chip area, but resistance and capacitance of power rails increase
Solution Approach 1:
By implementing backside power rail routing, the patent creates additional spatial dimensions for power distribution. This enables the power network to serve densely packed devices more effectively by providing multiple routing paths and reducing the length of individual power rails, thereby maintaining acceptable resistance and capacitance levels even as device density increases.
Solution Approach 2:
The patent segments the power distribution network into front-side and back-side components. This segmentation allows independent optimization of each layer's routing paths, enabling shorter and more efficient power delivery to densely packed devices while distributing the electrical load across multiple separated conductors on both substrate faces.
3Ease of manufacture
If conventional front-side power rail routing is used, then the manufacturing process is simpler, but yield loss increases and reliability decreases
Solution Approach 1:
The patent extends the power rail routing into the vertical dimension by utilizing the substrate back side. This dimensional expansion provides additional routing flexibility that improves electrical interconnection reliability and reduces yield loss, while the manufacturing process remains relatively straightforward by adapting existing front-side routing techniques to the back side of the substrate.
Data Source
AI summary
A method includes forming a doped region extending in a first direction on a substrate; depositing a gate electrode over the substrate and extending in a second direction; and forming a source/drain region on one side of the doped region; forming a first power rail over an upper surface of the source/drain region, the first power rail extending in the first direction and electrically coupled to the source/drain region; and depositing a second power rail below a lower surface of the source/drain region, the second power rail extending in the first direction and electrically coupled to the source/drain region. The first power rail overlap the second power rail from a top-view perspective.