Backside Power Delivery with Passive Die Stacking for Lower Parasitic Loss
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Solution Overview
Problem
Existing semiconductor devices suffer from parasitic losses that reduce power delivery performance due to non-ideal arrangements of power delivery configurations in semiconductor chips/dies.
Innovation Solution
A semiconductor device design that integrates a passive circuit die with 3D cylinder-type or crown-type capacitors on the backside of an active semiconductor die, reducing the distance between the passive circuit and the point of load, and utilizing hybrid bonding to enhance power delivery efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power delivery configuration uses conventional arrangement in semiconductor chips, then device structure is simple, but parasitic losses increase and power delivery performance deteriorates
Solution Approach 1:
The patent applies dimensionality change by moving the passive circuit die from the conventional planar arrangement to a vertical stacking configuration bonded to the backside of the active semiconductor die. This three-dimensional arrangement reduces the current path length and parasitic inductance by delivering power directly from the backside, thereby reducing parasitic losses while maintaining manageable device structure through standardized bonding processes
2Reliability
If passive circuit die is integrated on the backside of active die, then power delivery performance improves, but manufacturing process complexity increases
Solution Approach 1:
The patent applies segmentation by separating the semiconductor device into distinct functional modules: an active semiconductor die containing active components and a passive circuit die containing passive components. These segmented dies are manufactured independently using optimized processes for each function, then bonded together. This modular approach improves power delivery performance by reducing parasitic losses while managing manufacturing complexity through independent fabrication and assembly
3Loss of energy
If distance between passive circuit and point of load is reduced, then parasitic losses decrease, but device area allocation becomes more constrained
Solution Approach 1:
The patent resolves the area constraint by transitioning from a two-dimensional planar layout to a three-dimensional vertical stacking architecture. The passive circuit die is bonded to the backside of the active die, enabling power delivery components to be positioned immediately adjacent to the point of load in the vertical dimension. This reduces parasitic losses by minimizing current path length without consuming additional lateral device area, as the stacking utilizes the vertical space above and below the active die surface
Data Source
AI summary
A semiconductor device and a semiconductor package comprising the semiconductor device are provided. The semiconductor device comprises a first semiconductor die having a front side and a backside opposite to the front side and comprising first active components disposed adjacent to the front side of the first semiconductor die. The semiconductor device also comprises a second semiconductor die having a first side bonded to the backside of the first semiconductor die and a second side opposite to the first side. The second semiconductor die comprises passive components that are configured to manage a power delivery to the first semiconductor die.