Backside Power Rails for Denser Standard Cell Layouts
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Solution Overview
Problem
The challenge in semiconductor integrated circuit design is to reduce cell-to-cell spacing and cell height while avoiding shorting issues and congestion in the back-end-of-line (BEOL) interconnect design, particularly as the technology node scales down.
Innovation Solution
The implementation of a backside power distribution network and backside power rails, along with self-aligned dielectric isolation structures and forksheet field-effect transistor pairs, allows for reduced cell-to-cell spacing and cell height without compromising the integrity of the interconnect structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power rails are implemented in lower layers of BEOL interconnect structure, then power distribution is achieved, but lateral cell spacing must be increased to prevent shorting of adjacent source/drain contacts
Solution Approach 1:
The patent moves power rail connections from the lateral dimension (lower BEOL layers) to the vertical dimension (backside of substrate). By forming power rails and contacts on the backside of the semiconductor substrate, the design eliminates the need for lateral spacing between adjacent cells while maintaining reliable power distribution through vertical connections.
Solution Approach 2:
The patent inverts the conventional approach by placing power distribution infrastructure on the backside of the substrate rather than on the front side. This inversion allows power rails to be formed in the FEOL process module on the backside, enabling direct vertical connections to source/drain regions without interfering with lateral cell spacing requirements.
2Productivity
If cell height is reduced for higher integration density, then the number of pin access points for power and signal wiring decreases, but routeability is limited
Solution Approach 1:
The patent adds vertical routing capability by implementing backside power rails and contacts. This creates an additional dimension for signal and power distribution, allowing routes to go vertically through the substrate backside rather than being constrained to lateral routing in the front-side BEOL layers, thereby improving routeability despite reduced cell height.
Solution Approach 2:
The patent segments the power and signal distribution function into two separate dimensions: lateral distribution through front-side BEOL interconnects and vertical distribution through backside power rails. This segmentation allows independent optimization of each routing path, enabling reduced cell height while maintaining adequate routeability through the backside vertical connections.
3Reliability
If conventional FEOL buried power rails are formed with front-side via contacts, then power distribution is achieved, but additional lateral cell spacing is required for via contacts
Solution Approach 1:
The patent inverts the location of power rail formation from front-side to backside. By forming buried power rails on the backside of the substrate during FEOL processing, the design eliminates the need for front-side via contacts that would require additional lateral spacing. Power distribution is achieved through direct vertical connections from the backside power rails to the source/drain regions.
Data Source
AI summary
A device comprises a first interconnect structure, a second interconnect structure, a first cell comprising a first transistor, a second cell comprising a second transistor, a first contact connecting a source/drain element of the first transistor to the first interconnect structure, and second contact connecting a source/drain element of the second transistor to the second interconnect structure. The first cell is disposed adjacent to the second cell with the first transistor disposed adjacent to the second transistor. The first and second cells are disposed between the first and second interconnect structures.