Nanoinformatics TRIZ Cases
- Gate Spacer Structure for Replacement Gate Formation Precision
A gate spacer extending into the undercut region improves replacement gate formation precision while enhancing semiconductor electrical reliability.
- Quantum Gate Electrode Layout for Reduced Pitch Without EUV
Sequential gate and spacer formation cuts quantum circuit gate pitch to R/4 without EUV, improving qubit alignment and stability.
- Partitioned Source-Drain Contacts for 3D IC Power Delivery
Partitioned source-drain contacts enable top and bottom connections, easing 3D IC interconnect pitch limits while improving signal and power delivery.
- Transistor Gate Structure With Pure Work Function Metal Filling
Pure work function metal tuning layers fill narrow gate regions to lower resistance and threshold voltage in scaled nanostructure transistors.
- Stacked Channel Semiconductor Contacts for Higher Integration Density
A trench-filled contact and metal-semiconductor compound layer cut contact resistance in stacked channel devices while supporting higher integration density.
- GAA Metal Gate Patterning for Mixed Threshold Voltage Isolation
A two-step patterning and wet etch scheme isolates mixed Vt GAA gates while preventing metal gate retreat at 3 nm nodes.
- Metal Gate Fill Etching with ML Feedback for Thin-Film Precision
Machine learning adjusts metal gate etch conditions in real time to keep thin-film thickness and composition on target and reduce wafer scrap.
- Quantum Dot Readout Gate Layout for Parasitic Capacitance Isolation
An isolated two-gate accumulation layout improves quantum dot spin readout by reducing parasitic capacitance and enabling independent 2D electron gas control.
- Co-Doped Epitaxial Source/Drain Structures for Abrupt Dopant Profiles
In-situ phosphorus and arsenic co-doped epitaxy creates high-aspect-ratio source/drain regions with abrupt profiles, lower diffusion, and less p-to-n shorting.
- CFET Gate Dielectric Thickness Layout to Reduce NSH Erosion
A thicker top gate dielectric and thinner sidewalls protect CFET nanosheet stacks during etching while preserving process access.
- Transistor Isolation Below Source and Drain to Block Subfin Leakage
Insulator regions beneath the source and drain block parasitic subfin leakage in FinFET and gate-all-around transistors.
- RoW Transistor Stack Vt Tuning with Selective Dipole Shifters
Selective metal oxide diffusion shifts gate-insulator dipoles to tune threshold voltage across stacked RoW transistor channels.
- Vertically Stacked Channel FET With Ga-Doped High-Ge Source/Drain
Ga-doped high-Ge source/drain layers compress vertically stacked channels to improve electrical properties and reliability at higher integration.
- Dummy Fin Separation Structure for Source/Drain Isolation
Varying dummy fin widths balances etch loading to keep fin heights even, prevent source/drain merging, and support smaller standard cells.
- Carrier Wafer Debond Structure for Low-Damage Laser Separation
Alternating silicon and de-bond layers form resonant cavities for infrared laser ablation, enabling clean carrier wafer separation with minimal damage.
- SRAM Cell Layout With Backside Word Lines for Lower RC Loading
Separating word lines to the backside and bit lines to the front side cuts RC loading and coupling noise, improving SRAM speed and scaling.
- Core-Shell TFET Structure for Low-Leakage High On-State Current
Electrostatic band alignment in a core-shell TFET boosts on-state current while limiting leakage and power use in scaled semiconductor structures.
- Gate Contact Plug Structure for Fine-Pattern MOSFET Integration
A convex gate contact plug through dual capping layers helps fine-pattern MOSFETs improve integration, operating characteristics, and yield.
- Flip-Flop Clock Path Layout for Lower Power Interference
Orthogonal clock routing and gate conductors cut Miller capacitance between adjacent paths, reducing flip-flop power use by 7% to 11%.
- Backside Power Rails for Denser Standard Cell Layouts
Backside power rails shift power delivery off front-side BEOL layers, reducing cell spacing and height while improving routing and shorting isolation.
- hGAA Nanostructure Transistors With L-Shaped Active Regions
Complex L-shaped active regions in hGAA transistors enable flexible cell layouts and power savings while managing fine-pattern fabrication.