Co-Doped Epitaxial Source/Drain Structures for Abrupt Dopant Profiles
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Solution Overview
Problem
The challenge in integrated circuit fabrication is to achieve high aspect ratio n-type source or drain structures with abrupt dopant profiles, particularly for highly scaled transistor devices, while avoiding p-to-n shorting and maintaining device density and performance.
Innovation Solution
The implementation of in situ phosphorus (P) and arsenic (As) co-doped epitaxial source or drain structures, which utilize rapid {111} growth rates to achieve high height/width aspect ratios, thereby avoiding p-to-n shorting and enabling large contact areas through metal wrap-around.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional doping processes are used to create source or drain structures, then manufacturing simplicity is maintained, but dopant diffusion occurs resulting in non-abrupt dopant profiles
Solution Approach 1:
The patent changes the fundamental parameter of dopant introduction from post-growth implantation to in-situ doping during epitaxial growth. This enables abrupt dopant profiles because the dopants are incorporated during the crystal growth process itself, creating a sharp boundary at the growth interface without the diffusion that occurs with conventional thermal processes.
Solution Approach 2:
The dopants are introduced preliminarily during the epitaxial growth process rather than afterward. By incorporating phosphorus and arsenic during the silicon epitaxial growth, the dopant profile is established before any thermal processing that could cause diffusion, ensuring an abrupt profile is maintained through subsequent fabrication steps.
2Reliability
If high aspect ratio structures are formed to avoid p-to-n shorting, then device reliability improves, but manufacturing precision becomes more difficult to achieve
Solution Approach 1:
The patent exploits the parameter of crystal growth orientation by forming epitaxial structures on {111} oriented silicon surfaces. This orientation provides highly anisotropic growth characteristics, enabling the formation of high aspect ratio structures with precise dimensional control. The {111} orientation promotes vertical growth while suppressing lateral growth, naturally achieving high aspect ratios with excellent manufacturing precision.
3Productivity
If device dimensions are scaled down to increase density, then productivity improves, but maintaining mobility improvement and short channel control becomes more difficult
Solution Approach 1:
The patent employs composite doping with two different dopants (phosphorus and arsenic) in the same epitaxial layer. This composite approach provides synergistic effects: phosphorus contributes to carrier concentration while arsenic provides stronger strain effects that enhance carrier mobility. The combination maintains excellent short channel control and mobility improvement even as device dimensions are scaled down to increase density.
Solution Approach 2:
The patent changes the material parameter by incorporating strained silicon through the epitaxial growth process. The in-situ doped epitaxial silicon can be grown with controlled strain, and the {111} orientation provides inherent strain characteristics that improve carrier mobility. This parameter change enables maintaining performance at scaled dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved device performance and density by reducing defectivity and dopant diffusion, achieving a 20% improvement in resistivity and active carrier concentration compared to state-of-the-art nMOS source/drain materials.
Implementation Method 1
in situ phosphorus (P) and arsenic (As) co-doped epitaxial source or drain structures, which utilize rapid {111} growth rates to achieve high height/width aspect ratios
Implementation Method 2
achieving a 20% improvement in resistivity and active carrier concentration compared to state-of-the-art nMOS source/drain materials
Data Source
AI summary
Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.