Stacked Channel Semiconductor Contacts for Higher Integration Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices has led to a need for higher integration density, which existing technologies struggle to achieve effectively.
Innovation Solution
A semiconductor device design featuring a substrate with active patterns, channel layers, a gate structure, source/drain patterns with epitaxial layers, and contact structures, including a metal-semiconductor compound layer, to enhance electrical properties and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If higher integration density is pursued, then device performance and speed improve, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The device is divided into multiple channel layers (first channel layer, second channel layer, third channel layer) with different materials and functions. Each layer can be independently optimized and manufactured, allowing complex functionality to be achieved through modular assembly rather than monolithic complex processes
Solution Approach 2:
The patent transitions from planar 2D channels to vertically stacked 3D channels. Multiple channel layers are arranged in the vertical direction (perpendicular to substrate), enabling higher integration density without increasing lateral footprint, thus improving productivity while managing complexity through spatial reorganization
2Productivity
If more channel layers are stacked vertically, then integration density improves, but control of channel properties and electrical characteristics becomes more difficult
Solution Approach 1:
Different channel layers are assigned different material compositions and properties tailored to their specific functions. The first channel layer uses one material composition, the second channel layer uses another, and the third channel layer uses yet another. This allows each layer to be optimized for its local requirements, maintaining manufacturing precision even as vertical stacking increases integration density
Solution Approach 2:
The patent varies material parameters (composition, crystal structure, doping) across different channel layers to achieve desired electrical characteristics. By changing material parameters rather than relying solely on geometric control, the invention maintains precise control over channel properties while stacking multiple layers vertically
3Adaptability or versatility
If complex multi-layer channel structures are implemented, then device functionality improves, but manufacturing process steps and time increase
Solution Approach 1:
sacrificial layers are formed beforehand to define the positions and shapes of subsequent channel layers. These preliminary sacrificial structures guide the formation of complex multi-layer channels, enabling precise functionality to be achieved without adding excessive manufacturing steps or time
Solution Approach 2:
Multiple functions are integrated into a single unified device structure. The vertically stacked channel layers simultaneously provide multiple channels, different material properties, and enhanced functionality without requiring separate devices or additional processing time, thus improving adaptability while minimizing time loss
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed semiconductor device design improves electrical properties and integration density, enabling higher performance and speed while maintaining multifunctionality.
Implementation Method 1
both sides in the second direction of the source/drain pattern 150, and a metal-semiconductor compound layer 180 formed on the source/drain pattern 150 and the contact structure 190
Data Source
AI summary
A semiconductor device includes a substrate; an active pattern on the substrate; a plurality of channel layers stacked on the active pattern to be spaced apart from each other; a gate structure surrounding the plurality of channel layers; source/drain patterns including a first epitaxial layer disposed along side surfaces of the plurality of channel layers on a portion of the active pattern and a second epitaxial layer disposed on the first epitaxial layer and having a trench; contact structures disposed on the source/drain patterns, respectively, and including a first extension portion filling the trench, and a pair of second extension portions extending along both side surfaces of the source/drain patterns in the second direction, respectively; and a metal-semiconductor compound layer disposed between the source/drain patterns and the contact structures.