Quantum Gate Electrode Layout for Reduced Pitch Without EUV
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Solution Overview
Problem
The existing methods for manufacturing quantum electronic circuits with reduced gate pitch, necessary for precise manipulation of spin qubits, require expensive EUV lithography and are prone to variability and misalignment issues.
Innovation Solution
A method for manufacturing electronic circuits that achieves a final gate pitch of less than 80 nm by forming first, second, and third gate electrodes with a constant pitch, allowing for the insertion of third gate electrodes instead of spacers, thereby reducing the pitch by a factor of four without requiring EUV lithography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If EUV lithography is used to manufacture gates with pitch less than 25 nm, then manufacturing precision is improved, but device complexity and cost increase
Solution Approach 1:
The manufacturing process is segmented into multiple sequential steps: forming first gates at initial pitch, depositing spacers, forming second gates between first gates, removing spacers, and forming third gates between first and second gates. This multi-stage segmentation enables achieving 1/4 of the initial pitch using conventional DUV lithography instead of requiring EUV lithography, thus reducing device complexity and cost while maintaining manufacturing precision
Solution Approach 2:
Spacers are formed in advance between the first gates before the second gates are created. This preliminary action establishes the precise positioning framework that enables subsequent gates to be formed at the reduced pitch without requiring high-precision alignment during later steps, thereby reducing the complexity of lithography facilities needed
2Manufacturing precision
If gate pitch is reduced to less than 25 nm, then manufacturing precision is improved, but ease of manufacture deteriorates
Solution Approach 1:
The complex task of creating ultra-fine pitch gates is segmented into manageable steps using conventional lithography. Each step (forming first gates, adding spacers, forming second gates, forming third gates) uses standard DUV lithography processes, making the overall manufacturing easier and more accessible despite the final high precision requirement
Solution Approach 2:
Spacers serve as intermediary structures that facilitate the formation of second gates at reduced pitch. These spacers act as physical templates that simplify the alignment process, making the manufacturing of high-precision structures easier by providing a built-in positioning mechanism rather than relying solely on lithographic alignment
3Reliability
If gate pitch is reduced to counter electrostatic charge impact, then reliability is improved, but device complexity increases
Solution Approach 1:
The reliability improvement goal (reducing electrostatic charge impact) is achieved through segmented gate formation that enables reduced pitch without requiring complex EUV lithography. The multi-step process using conventional lithography maintains qubit location stability while avoiding the device complexity of advanced lithography facilities
Solution Approach 2:
The spacer structures are formed in advance to establish precise gate positioning before the actual gate electrodes are created. This preliminary positioning framework ensures reliable qubit locations (reduced electrostatic charge impact) while using simple, well-established manufacturing processes rather than complex advanced lithography
4Manufacturing precision
If gate pitch is reduced, then manufacturing precision is improved, but ease of operation deteriorates due to alignment difficulties
Solution Approach 1:
Spacers serve as intermediary positioning structures that simplify the alignment of electrical contacts to gates. The spacers provide a robust physical reference that makes aligning contacts easier, even though the final gate pitch is reduced, thereby improving ease of operation despite higher manufacturing precision requirements
Data Source
AI summary
A method for manufacturing an electronic circuit includes forming first electrodes distributed at a constant pitch; forming spacers against the first electrodes; forming a second electrode between two neighbouring spacers; and replacing each spacer with a third electrode. The first, second and third electrodes are thus distributed at an average pitch equal to R/4.