Core-Shell TFET Structure for Low-Leakage High On-State Current
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Solution Overview
Problem
As semiconductor devices shrink, challenges such as increased current leakage, signal crossover, and power consumption become significant, particularly due to the proximity of features, which existing tunneling field-effect transistors (TFETs) have not adequately addressed.
Innovation Solution
The proposed solution involves a semiconductor device structure that includes a core channel region between source/drain regions, a barrier layer adjacent to the core channel, and a shell energy band aligned with both the channel and barrier layers. This configuration allows for electrostatic modulation to align the energy bands, enhancing on-state current while minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional MOS field-effect transistors are used, then device scaling is achieved, but current leakage increases and power consumption rises
Solution Approach 1:
The patent changes the fundamental operating parameter of the transistor by transitioning from conventional MOSFET operation to TFET operation, utilizing band-to-band tunneling instead of thermionic emission. This parameter change enables sub-60mV/dec subthreshold swing, which directly reduces off-state leakage current while maintaining device scaling benefits
Solution Approach 2:
The patent employs composite material structures including heterojunctions (e.g., InAs/InAlAs, GaSb/AlSb) to create the TFET device. These composite materials enable precise control of band alignment and tunneling characteristics, achieving low leakage current while maintaining high on-state current through optimized conduction band offsets
2Area of moving object
If device features are made smaller and closer, then integration density increases, but signal crossover and current leakage worsen
Solution Approach 1:
The patent implements local quality control through selective doping regions (heavily doped source, lightly doped drain), varying shell thicknesses in nanowire structures, and localized barrier layer configurations. These local variations enable precise control of electric fields and carrier transport at each device region, preventing signal crossover while maintaining high integration density
Solution Approach 2:
The patent introduces intermediary structures such as shell layers in nanowire TFETs and barrier layers in heterojunction TFETs that act as mediators between source and drain regions. These intermediaries provide spatial separation and electrostatic control, preventing direct interaction between adjacent devices and reducing signal crossover effects
3Loss of energy
If tunneling field-effect transistors are used, then off-state leakage current is reduced, but on-state current is insufficient
Solution Approach 1:
The patent optimizes multiple parameters including shell thickness (5-20 nm), barrier layer composition and thickness, doping concentrations (10^18-10^20 atoms/cm³), and gate voltage to simultaneously achieve low off-state leakage and high on-state current. The conduction band offset is carefully controlled to enable sufficient tunneling probability in on-state while maintaining high barrier in off-state
Solution Approach 2:
The patent utilizes dynamic electrostatic control through the gate to modulate the tunneling barrier height and width. By applying different gate voltages, the energy band alignment is dynamically adjusted to enable high tunneling current in on-state and suppress tunneling in off-state, achieving both low leakage and high drive current
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The described configuration effectively increases the on-state current of semiconductor devices while maintaining low power consumption, addressing the challenges of current leakage and power usage in scaled semiconductor devices.
Implementation Method 1
a shell energy band aligned with both the channel and barrier layers. This configuration allows for electrostatic modulation to align the energy bands, enhancing on-state current while minimizing power consumption
Data Source
AI summary
A method includes the following steps. A substrate is etched, forming a core structure protruding out of a plane of the substrate. Shallow trench isolation (STI) features are formed on opposite sides of the core structure. The substrate and a lower portion of the core structure are doped to form a first source/drain region with a first doping concentration. A barrier layer is grown on an upper portion of the core structure. A first spacer is formed covering the STI features and covering the lower portion of core structure. A shell is formed wrapping the upper portion of the core structure and the barrier layer. The shell and the upper portion of the core structure have different doping conductivity types. A second source/drain region is formed with a second doping concentration over the shell. The first doping concentration and the second doping concentration are different from each other.