GAA Metal Gate Patterning for Mixed Threshold Voltage Isolation
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Solution Overview
Problem
The fabrication of FinFET devices with nanowires or nanosheets for gate-all-around (GAA) structures at technology nodes of 3 nm and below faces challenges in achieving mixed threshold voltages (Vts) boundary isolation due to difficulties in multiple patterning gates (MPGs) and metal gate material loss during wet etching.
Innovation Solution
A two-step patterning process and a two-step wet etching process are employed to achieve mixed Vts boundary isolation of multiple patterning gates. The two-step patterning process uses a first patterned mask inside the N/P boundary and a second patterned mask outside the boundary. The two-step wet etching process differentially removes the p-type work function layer in the n-type device region without metal gate material loss, thereby preventing metal gate retreat along the N/P boundary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single-step patterning process is used for multiple patterning gates, then the fabrication process is simpler, but mixed threshold voltage boundary isolation cannot be achieved
Solution Approach 1:
The patterning process is divided into two distinct steps: first forming a preliminary gate pattern, then forming a second pattern that creates the mixed threshold voltage regions. This segmentation allows precise control over boundary isolation between n-type and p-type device regions while maintaining process feasibility
Solution Approach 2:
The first patterning step creates a preliminary gate structure that serves as a foundation for the second patterning step. This preliminary action establishes the basic gate layout before the more precise second pattern is applied, enabling better control over the final mixed threshold voltage boundary
2Productivity
If conventional wet etching is used, then the etching process is faster, but metal gate material is lost causing gate retreat
Solution Approach 1:
A protective mask layer is introduced as an intermediary between the wet etchant and the metal gate material. This mask layer allows the wet etching process to proceed at high speed while preventing etchant contact with the metal gate, thereby eliminating material loss and gate retreat while maintaining fast processing
Solution Approach 2:
The potentially harmful effect of wet etchant on metal gate material is converted into a benefit by using the etchant's high speed and selectivity to remove sacrificial layers and dielectric materials, while the protective mask prevents any damage to the metal gate. The harmful etchant becomes a useful tool when properly controlled
3Quantity of substance
If device feature sizes are reduced for higher density, then device density increases, but fabrication difficulty increases
Solution Approach 1:
The invention changes the parameter of patterning methodology from single-step to two-step process, which enables precise control at reduced feature sizes. This parameter change in the fabrication approach allows high device density to be achieved while managing the increased fabrication complexity through systematic process division
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a plurality of first nanostructures formed over a substrate, and a plurality of second nanostructures formed over the substrate. The semiconductor device includes a gate structure surrounding the first nanostructures and the second nanostructures, and the first hard mask layer and the second hard mask layer are surrounded by the gate dielectric layer. The semiconductor device includes an isolation structure extending upwardly above the substrate, and a bottom surface of the isolation structure is lower than a bottommost surface of the gate structure.