CFET Gate Dielectric Thickness Layout to Reduce NSH Erosion
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Solution Overview
Problem
The fabrication of complementary field effect transistor (CFET) devices faces challenges in depositing a gate oxide layer that wraps around the nanosheet stack without damaging it, leading to 'NSH erosion' which reduces device performance.
Innovation Solution
A method involving the formation of fin structures with a gate dielectric layer having a non-uniform thickness, where the layer thickness on the top surface is greater than on the side surfaces, providing enhanced protection against subsequent fabrication steps and reducing NSH erosion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a thin gate oxide layer is deposited around the nanosheet stack, then the gate oxide can be successfully formed without excessive damage to the NSH stack, but the protection against subsequent fabrication steps (e.g., full gate etching) is insufficient, leading to NSH erosion
Solution Approach 1:
The patent applies local quality by creating a non-uniform gate oxide layer with different thicknesses at different locations: a first thickness on the top surface of the fin structure and a second (thinner) thickness on the side surfaces. This allows the top surface to provide erosion protection while the side surfaces enable adequate gate oxide breakthrough, resolving the contradiction between protection and manufacturability
Solution Approach 2:
The patent transitions from a uniform two-dimensional gate oxide layer to a three-dimensional non-uniform structure with varying thickness across different surfaces of the fin structure. This dimensional approach allows simultaneous optimization of protection (top surface) and access (side surfaces)
2Reliability
If a thick gate oxide layer is deposited on the top surface of the fin structure, then protection against NSH erosion during full gate etching is improved, but the space between adjacent fin structures becomes insufficient for performing further processing steps
Solution Approach 1:
The patent implements local quality by assigning different gate oxide thicknesses to different functional regions: the top surface receives a thicker layer for erosion protection, while the side surfaces receive a thinner layer to maintain accessibility for subsequent processing steps between adjacent fin structures
Solution Approach 2:
The gate oxide layer is segmented into distinct thickness regions based on location: a first thickness region on top surfaces and a second thickness region on side surfaces. This segmentation allows each region to be optimized for its specific function without compromising the other
3Ease of manufacture
If a uniform gate oxide layer is deposited around the fin structure, then the deposition process is simpler, but it cannot simultaneously provide adequate protection on top surfaces and maintain access on side surfaces
Solution Approach 1:
The patent resolves this contradiction by applying local quality - the gate oxide layer is deposited with locally optimized thickness: thicker on top surfaces for protection and thinner on side surfaces for accessibility. This can be achieved through controlled deposition processes that account for surface orientation and subsequent selective etching
Solution Approach 2:
The patent introduces asymmetry in the gate oxide layer thickness distribution, creating a non-uniform structure where the thickness varies by location and orientation. This asymmetric design allows the structure to fulfill multiple conflicting requirements that a symmetric uniform layer cannot satisfy
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively protects the fin structure from damage during subsequent fabrication steps, reducing NSH erosion and enhancing the overall performance of the CFET device.
Implementation Method 1
the gate dielectric layer is deposited on the at least one fin structure by means of a layer deposition technique, such as plasma enhanced atomic layer deposition (PEALD) or pulsed chemical vapor deposition (CVD)
Implementation Method 2
the gate dielectric layer is deposited on the at least one fin structure by means of a layer deposition technique, such as plasma enhanced atomic layer deposition (PEALD) or pulsed chemical vapor deposition (CVD)
Data Source
Figure 1A~1D
Figure 2A~2B
Figure 3A~3B
AI summary
The disclosure relates to a method for processing a complementary field effect transistor, CFET, device. The method comprises the steps of: forming at least one fin structure (23) on a substrate (14), wherein the at least one fin structure (23) comprises a horizontal top surface and two vertically oriented side surfaces between the top surface and the substrate (14), and wherein the at least one fin structure (23) comprises a first layer stack (23a) and a second layer stack (23b) above the first layer stack (23a); and forming a gate dielectric layer (41) with a nonuniform layer thickness around the at least one fin structure (23); wherein the layer thickness of the gate dielectric layer (41) which is arranged on the top surface of the at least one fin structure (23) is larger than the layer thickness of the gate dielectric layer (41) which is arranged on the side surfaces of the at least one fin structure (23).